F-RAM Memory. FM28V100 Datasheet

FM28V100 Memory. Datasheet pdf. Equivalent

FM28V100 Datasheet
Recommendation FM28V100 Datasheet
Part FM28V100
Description 1-Mbit (128 K x 8) F-RAM Memory
Feature FM28V100; FM28V100 1-Mbit (128 K × 8) F-RAM Memory 1-Mbit (128 K × 8) F-RAM Memory Features ■ 1-Mbit ferroele.
Manufacture Cypress Semiconductor
Datasheet
Download FM28V100 Datasheet




Cypress Semiconductor FM28V100
FM28V100
1-Mbit (128K × 8) F-RAM Memory
1-Mbit (128K × 8) F-RAM Memory
Features
1-Mbit ferroelectric random access memory (F-RAM) logically
organized as 128K × 8
High-endurance 100 trillion (1014) read/writes
151-year data retention (see Data Retention and Endurance
on page 7)
NoDelay™ writes
Page mode operation to 30 ns cycle time
Advanced high-reliability ferroelectric process
SRAM compatible
Industry-standard 128K × 8 SRAM pinout
60-ns access time, 90-ns cycle time
Superior to battery-backed SRAM modules
No battery concerns
Monolithic reliability
True surface mount solution, no rework steps
Superior for moisture, shock, and vibration
Low power consumption
Active current 7 mA (typ)
Standby current 90 A (typ)
Low-voltage operation: VDD = 2.0 V to 3.6 V
Industrial temperature: –40 C to +85 C
Logic Block Diagram
32-pin thin small outline package (TSOP) Type I
Restriction of hazardous substances (RoHS) compliant
Functional Description
The FM28V100 is a 128K × 8 nonvolatile memory that reads and
writes similar to a standard SRAM. A ferroelectric random
access memory or F-RAM is nonvolatile, which means that data
is retained after power is removed. It provides data retention for
over 151 years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing and high
write endurance make the F-RAM superior to other types of
memory.
The FM28V100 operation is similar to that of other RAM devices
and therefore, it can be used as a drop-in replacement for a
standard SRAM in a system. Read and write cycles may be
triggered by chip enable or simply by changing the address. The
F-RAM memory is nonvolatile due to its unique ferroelectric
memory process. These features make the FM28V100 ideal for
nonvolatile memory applications requiring frequent or rapid
writes.
The device is available in a 32-pin TSOP I surface mount
package. Device specifications are guaranteed over the
industrial temperature range –40 °C to +85 °C.
For a complete list of related documentation, click here.
A16-0
CE 1, CE2
WE
OE
A 16-3
A 2-0
Control
Logic
128 K x 8
F-RAM Array
...
Column Decoder
I/O Latch & Bus Driver
DQ 7-0
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-86202 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 20, 2018



Cypress Semiconductor FM28V100
FM28V100
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
Memory Operation ....................................................... 4
Read Operation ........................................................... 4
Write Operation ........................................................... 4
Page Mode Operation ................................................. 4
Pre-charge Operation .................................................. 4
SRAM Drop-In Replacement ....................................... 5
Maximum Ratings ............................................................. 6
Operating Range ............................................................... 6
DC Electrical Characteristics .......................................... 6
Data Retention and Endurance ....................................... 7
Capacitance ...................................................................... 7
Thermal Resistance .......................................................... 7
AC Test Conditions .......................................................... 7
AC Switching Characteristics ......................................... 8
SRAM Read Cycle ...................................................... 8
SRAM Write Cycle ....................................................... 9
Power Cycle Timing ....................................................... 12
Functional Truth Table ................................................... 13
Ordering Information ...................................................... 14
Ordering Code Definitions ......................................... 14
Package Diagrams .......................................................... 15
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC® Solutions ...................................................... 18
Cypress Developer Community ................................. 18
Technical Support ..................................................... 18
Document Number: 001-86202 Rev. *G
Page 2 of 18



Cypress Semiconductor FM28V100
FM28V100
Pinout
A11
A9
A8
A13
WE
CE2
A15
VNDCD[1]
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Figure 1. 32-pin TSOP I pinout
32-pin TSOP I
(x 8)
Top view
(not to scale)
32 OE
31 A10
30 CE1
29 DQ7
28 DQ6
27 DQ5
26 DQ4
25 DQ3
24 VSS
23 DQ2
22 DQ1
21 DQ0
20 A0
19 A1
18 A2
17 A3
Pin Definitions
Pin Name I/O Type
Description
A16–A0
DQ7–DQ0
WE
Input
Address inputs: The 17 address lines select one of 131,072 bytes in the F-RAM array. The lowest two
address lines A2–A0 may be used for page mode read and write operations.
Input/Output Data I/O Lines: 8-bit bidirectional data bus for accessing the F-RAM array.
Input
Write Enable: A write cycle begins when WE is asserted. The rising edge causes the FM28V100 to write
the data on the DQ bus to the F-RAM array. The falling edge of WE latches a new column address for
page mode write cycles.
CE1, CE2
Input
Chip Enable: The device is selected and a new memory access begins on the falling edge of CE1 (while
CE2 is HIGH) or the rising edge of CE2 (while CE1 is LOW). The entire address is latched internally at
this point. The CE2 pin is pulled up internally. Subsequent changes to the A2–A0 address inputs allow
page mode operation.
OE Input Output Enable: When OE is LOW, the FM28V100 drives the data bus when the valid read data is
available. Deasserting OE HIGH tristates the DQ pins.
VSS Ground Ground for the device. Must be connected to the ground of the system.
VDD Power supply Power supply input to the device.
NC No connect No connect. This pin is not connected to the die.
Note
1. Reserved for address A17 on 2-Mbit device.
Document Number: 001-86202 Rev. *G
Page 3 of 18







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