Flow-Through SRAM. CY7C1461KV33 Datasheet

CY7C1461KV33 SRAM. Datasheet pdf. Equivalent

CY7C1461KV33 Datasheet
Recommendation CY7C1461KV33 Datasheet
Part CY7C1461KV33
Description 36-Mbit (1M x 36/2M x 18) Flow-Through SRAM
Feature CY7C1461KV33; CY7C1461KV33 CY7C1463KV33 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture 36-Mb.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C1461KV33 Datasheet




Cypress Semiconductor CY7C1461KV33
CY7C1461KV33
CY7C1463KV33
36-Mbit (1M × 36/2M × 18) Flow-Through SRAM
with NoBL™ Architecture
36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture
Features
No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
Supports up to 133 MHz bus operations with zero wait states
Data is transferred on every clock
Pin compatible and functionally equivalent to ZBT™ devices
Internally self timed output buffer control to eliminate the need
to use OE
Registered inputs for flow through operation
Byte write capability
3.3 V and 2.5 V I/O power supply
Fast clock-to-output times
6.5 ns (for 133-MHz device)
Clock Enable (CEN) pin to enable clock and suspend operation
Synchronous self timed writes
Asynchronous Output Enable
CY7C1461KV33,
CY7C1463KV33
available
JEDEC-standard Pb-free 100-pin TQFP packages
in
Three chip enables for simple depth expansion
Automatic power down feature available using ZZ mode or CE
deselect
Burst capability – linear or interleaved burst order
Low standby power
Functional Description
The CY7C1461KV33/CY7C1463KV33 are 3.3 V,
1M × 36/2M × 18 Synchronous Flow-Through Burst SRAMs
designed specifically to support unlimited true back-to-back read
and write operations without the insertion of wait states. The
CY7C1461KV33/CY7C1463KV33 is equipped with the advanced
NoBL logic required to enable consecutive read and write
operations with data being transferred on every clock cycle. This
feature dramatically improves the throughput of data through the
SRAM, especially in systems that require frequent write-read
transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133 MHz device).
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
Selection Guide
Maximum access time
Maximum operating current
Description
133 MHz Unit
6.5 ns
× 18 150 mA
× 36 170
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-66681 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 7, 2016



Cypress Semiconductor CY7C1461KV33
CY7C1461KV33
CY7C1463KV33
Logic Block Diagram – CY7C1461KV33
A0, A1, A
MODE
CLK C
CEN
CE
ADV/LD
BW A
BW B
BW C
BW D
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER
A1
A0
D1
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
BURST
LOGIC
Q1
Q0
A1'
A0'
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
READ LOGIC
SLEEP
CONTROL
INPUT E
REGISTER
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
NE
G
DQs
DQP A
DQP B
DQP C
DQP D
Document Number: 001-66681 Rev. *G
Page 2 of 23



Cypress Semiconductor CY7C1461KV33
CY7C1461KV33
CY7C1463KV33
Logic Block Diagram – CY7C1463KV33
A0, A1, A
MODE
CLK C
CEN
CE
ADDRESS
REGISTER
A1
A0
D1
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
BURST
LOGIC
Q1
Q0
A1'
A0'
ADV/LD
BW A
BW B
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
OE
CE1
READ LOGIC
CE2
CE3
ZZ
SLEEP
CONTROL
INPUT E
REGISTER
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
NE
G
DQs
DQP A
DQP B
Document Number: 001-66681 Rev. *G
Page 3 of 23







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