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CY7C1463KV33 Dataheets PDF



Part Number CY7C1463KV33
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description 36-Mbit (1M x 36/2M x 18) Flow-Through SRAM
Datasheet CY7C1463KV33 DatasheetCY7C1463KV33 Datasheet (PDF)

CY7C1461KV33 CY7C1463KV33 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture Features ■ No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles ■ Supports up to 133 MHz bus operations with zero wait states ❐ Data is transferred on every clock ■ Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self timed output buffer control to eliminate the need to us.

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CY7C1461KV33 CY7C1463KV33 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture Features ■ No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles ■ Supports up to 133 MHz bus operations with zero wait states ❐ Data is transferred on every clock ■ Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self timed output buffer control to eliminate the need to use OE ■ Registered inputs for flow through operation ■ Byte write capability ■ 3.3 V and 2.5 V I/O power supply ■ Fast clock-to-output times ❐ 6.5 ns (for 133-MHz device) ■ Clock Enable (CEN) pin to enable clock and suspend operation ■ Synchronous self timed writes ■ Asynchronous Output Enable ■ CY7C1461KV33, CY7C1463KV33 available JEDEC-standard Pb-free 100-pin TQFP packages in ■ Three chip enables for simple depth expansion ■ Automatic .


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