Pipelined SRAM. CY7C1470BV33 Datasheet

CY7C1470BV33 SRAM. Datasheet pdf. Equivalent

CY7C1470BV33 Datasheet
Recommendation CY7C1470BV33 Datasheet
Part CY7C1470BV33
Description 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM
Feature CY7C1470BV33; CY7C1470BV33 CY7C1472BV33 CY7C1474BV33 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C1470BV33 Datasheet





Cypress Semiconductor CY7C1470BV33
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
72-Mbit (2 M × 36/4 M × 18/1 M × 72)
Pipelined SRAM with NoBL™ Architecture
72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture
Features
Pin-compatible and functionally equivalent to ZBT™
Supports 250 MHz bus operations with zero wait states
Available speed grades are 250, 200, and 167 MHz
Internally self timed output buffer control to eliminate the need
to use asynchronous OE
Fully registered (inputs and outputs) for pipelined operation
Byte Write capability
Single 3.3 V power supply
3.3 V/2.5 V I/O power supply
Fast clock-to-output time
3.0 ns (for 250 MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self timed writes
CY7C1470BV33,
CY7C1472BV33
available
in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package. CY7C1474BV33
available in Pb-free and non-Pb-free 209-ball FBGA package
IEEE 1149.1 JTAG Boundary Scan compatible
Burst capability – linear or interleaved burst order
“ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
are 3.3 V, 2 M × 36/4 M × 18/1 M × 72 Synchronous pipelined
burst SRAMs with No Bus Latency™ (NoBL logic,
respectively. They are designed to support unlimited true
back-to-back read or write operations with no wait states. The
CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are
equipped with the advanced (NoBL) logic required to enable
consecutive read or write operations with data being transferred
on every clock cycle. This feature dramatically improves the
throughput of data in systems that require frequent read or write
transitions. The CY7C1470BV33, CY7C1472BV33, and
CY7C1474BV33 are pin compatible and functionally equivalent
to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the Clock Enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the Byte Write Selects
(BWa–BWd for CY7C1470BV33, BWa–BWb for
CY7C1472BV33, and BWa–BWh for CY7C1474BV33) and a
Write Enable (WE) input. All writes are conducted with on-chip
synchronous self timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
250 MHz
3.0
500
120
200 MHz
3.0
500
120
167 MHz
3.4
450
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-15031 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 20, 2014



Cypress Semiconductor CY7C1470BV33
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Logic Block Diagram – CY7C1470BV33
A0, A1, A
MODE
CLK C
CEN
ADV/LD
BW a
BW b
BW c
BW d
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
INPUT
REGISTER 1 E
O
U
T
P
U
T
D
A
T
A
O
U
T
P
U
T
R
E
S
B
G
I
S
T
E
R
S
E
T
E
E
R
I
N
U
F
F
E
R
S
E
G
INPUT
REGISTER 0 E
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
READ LOGIC
SLEEP
CONTROL
Logic Block Diagram – CY7C1472BV33
A0, A1, A
MODE
CLK C
CEN
ADV/LD
BW a
BW b
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
O
U
T
S
E
N
P
U
T
MEMORY
ARRAY
S
E
A
M
P
S
R
E
G
I
S
T
E
R
S
E
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
N
G
E
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
DQ s
DQ Pa
DQ Pb
READ LOGIC
Sleep
Control
Document Number: 001-15031 Rev. *M
Page 2 of 34



Cypress Semiconductor CY7C1470BV33
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Logic Block Diagram – CY7C1474BV33
A0, A1, A
MODE
CLK C
CEN
ADV/LD
BW a
BW b
BW c
BW d
BW e
BW f
BW g
BW h
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
O
U
T
S
E
N
P
U
T
MEMORY
ARRAY
S
E
A
M
P
S
R
E
G
I
S
T
E
R
S
E
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
N
G
E
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
DQ Pe
DQ Pf
DQ Pg
DQ Ph
READ LOGIC
Sleep
Control
Document Number: 001-15031 Rev. *M
Page 3 of 34





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