CY7C1471BV25

CY7C1471BV25 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture 72-Mbit (2 M × 36/1 M × 72) Flow-Through SRAM with NoBL™ Architecture Features ■ No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles ■ Supports up to 133 MHz bus operations with zero wait states ■ Data transfers on every clock ■ Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self timed output buffer control to eliminate the need to use OE ■ Registered inputs for flow through operation ■ Byte Write capability ■ 2.5-V I/O supply (VDDQ) ■ Fast clock-to-output times ❐ 6.5 ns (for 133-MHz device) ■ Clock Enable (CEN) pin to enable clock and suspend operation ■ Synchronous self timed writes ■ Asynchronous Output Enable (OE) ■ CY7C1471BV25 available in JEDEC-standard Pb-free 100-pin TQFP package. ■ Three Chip Enables (CE1, CE2, CE3) for simple depth expansion. ■ Automatic power down feature available using ZZ mod...