CY7C1473BV33

CY7C1471BV33 CY7C1473BV33 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture Features ■ No bus latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles ■ Supports up to 133 MHz bus operations with zero wait states ■ Data is transferred on every clock ■ Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self timed output buffer control to eliminate the need to use OE ■ Registered inputs for flow through operation ■ Byte write capability ■ 3.3 V/2.5 V I/O supply (VDDQ) ■ Fast clock-to-output times ❐ 6.5 ns (for 133 MHz device) ■ Clock enable (CEN) pin to enable clock and suspend operation ■ Synchronous self-timed writes ■ Asynchronous output enable (OE) ■ CY7C1471BV33 available in JEDEC-standard Pb-free 100-pin thin quad flat pack (TQFP), Pb-free and non-Pb-free 165-ball fine-pitch ball grid array (FBGA) package...