Flow-Through SRAM. CY7C1441KV33 Datasheet

CY7C1441KV33 SRAM. Datasheet pdf. Equivalent

CY7C1441KV33 Datasheet
Recommendation CY7C1441KV33 Datasheet
Part CY7C1441KV33
Description 36-Mbit (1M x 36/2M x 18) Flow-Through SRAM
Feature CY7C1441KV33; CY7C1441KV33 CY7C1443KV33 CY7C1441KVE33 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM (With ECC) 36-M.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C1441KV33 Datasheet




Cypress Semiconductor CY7C1441KV33
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
36-Mbit (1M × 36/2M × 18)
Flow-Through SRAM (With ECC)
36-Mbit (1M × 36/2M × 18) Flow-Through SRAM (With ECC)
Features
Supports 133-MHz bus operations
1M × 36/2M × 18 common I/O
3.3 V core power supply
2.5 V or 3.3 V I/O power supply
Fast clock-to-output times
6.5 ns (133 MHz version)
Provide high-performance 2-1-1-1 access rate
User-selectable burst counter supporting IntelPentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous output enable
CY7C1441KV33, CY7C1443KV33, and CY7C1441KVE33 are
available in JEDEC-standard 100-pin TQFP and 165-ball
FBGA Pb-free packages.
IEEE 1149.1 JTAG-Compatible Boundary Scan
“ZZ” Sleep Mode option
On-chip error correction code (ECC) to reduce soft error rate
(SER)
Functional Description
The CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33 are
3.3 V, 1M × 36/2M × 18/1M × 36 synchronous flow-through
SRAMs, respectively designed to interface with high-speed
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip
counter captures the first address in a burst and increments the
address automatically for the rest of the burst access. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock (CLK) input. The synchronous
inputs include all addresses, all data inputs, address-pipelining
Chip Enable (CE1), depth-expansion Chip Enables (CE2 and
CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (BWx, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the ZZ
pin.
The CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33 allow
either interleaved or linear burst sequences, selected by the
MODE input pin. A HIGH selects an interleaved burst sequence,
while a LOW selects a linear burst sequence. Burst accesses
can be initiated with the Processor Address Strobe (ADSP) or the
cache Controller Address Strobe (ADSC) inputs. Address
advancement is controlled by the Address Advancement (ADV)
input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
The CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33
operate from a +3.3 V core power supply while all outputs may
operate with either a +2.5 V or +3.3 V supply. All inputs and
outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
Maximum access time
Maximum operating current
Description
× 18
× 36
133 MHz
6.5
150
170
Unit
ns
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-66677 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 15, 2018



Cypress Semiconductor CY7C1441KV33
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Logic Block Diagram – CY7C1441KV33
A 0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW D
BW C
BW B
BW A
BWE
GW
CE1
CE2
CE3
OE
ZZ
ADDRESS
REGISTER
A [1:0]
BURST Q1
COUNTER
AND LOGIC
CLR Q0
DQ D, DQP D
BYTE
WRITE REGISTER
DQ C, DQP C
BYTE
WRITE REGISTER
DQ B, DQP B
BYTE
WRITE REGISTER
DQ A, DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
SLEEP
CONTROL
Logic Block Diagram – CY7C1443KV33
A 0,A1,A
MODE
ADV
CLK
ADSC
ADSP
BW B
BW A
BWE
GW
CE 1
CE 2
CE 3
OE
ZZ
ADDRESS
REGISTER
A[1:0]
BURST Q1
COUNTER AND
LOGIC
CLR Q0
DQ B,DQP B
WRITE REGISTER
DQ A,DQP A
WRITE REGISTER
ENABLE
REGISTER
SLEEP
CONTROL
DQ D, DQP D
BYTE
WRITE REGISTER
DQ C, DQP C
BYTE
WRITE REGISTER
DQ B, DQP B
BYTE
WRITE REGISTER
DQ A, DQP A
BYTE
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQ s
DQP A
DQP B
DQP C
DQP D
INPUT
REGISTERS
DQ B,DQP B
WRITE DRIVER
DQ A,DQP A
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQP A
DQP B
INPUT
REGISTERS
Document Number: 001-66677 Rev. *I
Page 2 of 32



Cypress Semiconductor CY7C1441KV33
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Logic Block Diagram – CY7C1441KVE33
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BWD
BWC
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ZZ
ADDRESS
REGISTER
A[1:0]
BURST Q1
COUNTER
AND LOGIC
CLR Q0
DQD, DQPD
BYTE
WRITE REGISTER
DQC, DQPC
BYTE
WRITE REGISTER
DQB, DQPB
BYTE
WRITE REGISTER
DQA, DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
SLEEP
CONTROL
DQD, DQPD
BYTE
WRITE REGISTER
DQC, DQPC
BYTE
WRITE REGISTER
DQB, DQPB
BYTE
WRITE REGISTER
DQA, DQPA
BYTE
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
ECC
DECODER
OUTPUT
BUFFERS
DQs
DQPA
DQPB
DQPC
DQPD
ECC
ENCODER
INPUT
REGISTERS
Document Number: 001-66677 Rev. *I
Page 3 of 32







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