Dual-Port RAM. CYD02S36V Datasheet

CYD02S36V RAM. Datasheet pdf. Equivalent

CYD02S36V Datasheet
Recommendation CYD02S36V Datasheet
Part CYD02S36V
Description 3.3 V (64 K x 36) Synchronous Dual-Port RAM
Feature CYD02S36V; CYD02S36V/36VA FLEx36™ 3.3 V (64 K × 36) Synchronous Dual-Port RAM FLEx36™ 3.3 V (64 K × 36) Synchr.
Manufacture Cypress Semiconductor
Datasheet
Download CYD02S36V Datasheet




Cypress Semiconductor CYD02S36V
CYD02S36V/36VA
FLEx36™ 3.3 V (64 K × 36) Synchronous
Dual-Port RAM
FLEx36™ 3.3 V (64 K × 36) Synchronous Dual-Port RAM
Features
True dual-ported memory cells that enable simultaneous
access of the same memory location
Synchronous pipelined operation
Pipelined output mode allows fast operation
0.18 micron complementary metal oxide semiconductor
(CMOS) for optimum speed and power
High speed clock to data access
3.3 V low power
Active as low as 225 mA (typ.)
Standby as low as 55 mA (typ.)
Mailbox function for message passing
Global master reset
Separate byte enables on both ports
Commercial and industrial temperature ranges
IEEE 1149.1-compatible joint test action group (JTAG)
boundary scan
256 Ball fine-pitch ball grid array (FBGA) (1-mm pitch)
Counter wrap around control
Internal mask register controls counter wrap-around
Counter-interrupt flags to indicate wrap-around
Memory block retransmit operation
Counter readback on address lines
Mask register readback on address lines
Dual chip enables on both ports for easy depth expansion
Seamless migration to next-generation dual-port family
Product Selection Guide
Density
Part number
Max. speed (MHz)
Max. access time – clock to data (ns)
Typical operating current (mA)
Package
Functional Description
The FLEx36™ family includes 2-Mbit pipelined, synchronous,
true dual-port static RAMs that are high speed, low power 3.3 V
CMOS. Two ports are provided, permitting independent,
simultaneous access to any location in memory. A particular port
can write to a certain location while another port is reading that
location. The result of writing to the same location by more than
one port at the same time is undefined. Registers on control,
address, and data lines allow for minimal setup and hold time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
Seamless Migration to Next-Generation Dual-Port
Family
Cypress offers a migration path for all devices in this family to the
next-generation devices in the Dual-Port family with a compatible
footprint. Please contact Cypress Sales for more details.
For a complete list of related documentation, click here.
2-Mbit
(64 K × 36)
CYD02S36V/36VA
167
4.4
225
256 FBGA
(17 mm x 17 mm)
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06076 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 27, 2014



Cypress Semiconductor CYD02S36V
Logic Block Diagram
FTSELL
PORTSTD[1:0]L
DQ [35:0]L
BE [3:0]L
CE0L
CE1L
OEL
R/WL
CONFIG Block
IO
Control
CYD02S36V/36VA
CONFIG Block
IO
Control
FTSELR
PORTSTD[1:0]R
DQ [35:0]R
BE [3:0]R
CCEE01RR
OER
R/WR
Dual Ported Array
A [15:0]L
CNATD/MSLSKL
CNTENL
CNTRSTL
RETL
CNTINTL
CL
WRPL
INTL
BUSYL
Arbitration Logic
BUSYR
Address &
Counter Logic
Address &
Counter Logic
Mailboxes
INTR
READYL
LowSPDL
JTAG
RESET
LOGIC
A [15:0]R
CNCATND/TMSESRNKRR
CNTRSTR
RETR
CNCTIRNTR
WRPR
TRST
TMS
TDI
TDO
TCK
MRST
READYR
LowSPDR
Document Number: 38-06076 Rev. *M
Page 2 of 29



Cypress Semiconductor CYD02S36V
CYD02S36V/36VA
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Master Reset ..................................................................... 6
Mailbox Interrupts ............................................................ 6
Address Counter and Mask Register Operations .......... 6
Counter Reset Operation ............................................ 7
Counter Load Operation .............................................. 7
Counter Increment Operation ...................................... 8
Counter Hold Operation .............................................. 8
Counter Interrupt ......................................................... 8
Counter Readback Operation ...................................... 8
Retransmit ................................................................... 8
Mask Reset Operation ................................................. 8
Mask Load Operation .................................................. 8
Mask Readback Operation .......................................... 8
Counting by Two ......................................................... 8
IEEE 1149.1 Serial Boundary Scan (JTAG)[18] .............. 10
Performing a TAP Reset ........................................... 10
Performing a Pause/Restart ...................................... 10
Maximum Ratings ........................................................... 12
Operating Range ............................................................. 12
Electrical Characteristics ............................................... 12
Capacitance .................................................................... 12
Switching Characteristics .............................................. 13
JTAG Timing ................................................................... 14
JTAG Switching Waveform ............................................ 15
Switching Waveforms .................................................... 15
Ordering Information ...................................................... 25
64 K × 36 (2-Mbit) 3.3 V
Synchronous CYD02S36V Dual-Port SRAM .................... 25
Ordering Code Definitions ......................................... 25
Package Diagram ............................................................ 26
Acronyms ........................................................................ 27
Document Conventions ................................................. 27
Units of Measure ....................................................... 27
Document History Page ................................................. 28
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support ....................... 29
Products .................................................................... 29
PSoC® Solutions ...................................................... 29
Cypress Developer Community ................................. 29
Technical Support ..................................................... 29
Document Number: 38-06076 Rev. *M
Page 3 of 29







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