HP SRAM. CY7C4141KV13 Datasheet

CY7C4141KV13 SRAM. Datasheet pdf. Equivalent

CY7C4141KV13 Datasheet
Recommendation CY7C4141KV13 Datasheet
Part CY7C4141KV13
Description 144-Mbit QDR-IV HP SRAM
Feature CY7C4141KV13; CY7C4121KV13/CY7C4141KV13 144-Mbit QDR™-IV HP SRAM 144-Mbit QDR™-IV HP SRAM Features ■ 144-Mbit den.
Manufacture Cypress Semiconductor
Download CY7C4141KV13 Datasheet

Cypress Semiconductor CY7C4141KV13
144-Mbit QDR™-IV HP SRAM
144-Mbit QDR™-IV HP SRAM
144-Mbit density (8M ×18, 4M ×36)
Total Random Transaction Rate [1] of 1334 MT/s
Maximum operating frequency of 667 MHz
Read latency of 5.0 clock cycles and write latency of 3.0 clock
Two-word burst on all accesses
Dual independent bidirectional data ports
Double data rate (DDR) data ports
Supports concurrent read/write transactions on both ports
Single address port used to control both data ports
DDR address signaling
Single data rate (SDR) control signaling
High-speed transceiver logic (HSTL) and stub series
terminated logic (SSTL) compatible signaling (JESD8-16A
I/O VDDQ = 1.2 V ± 50 mV or 1.25 V ± 50 mV
Pseudo open drain (POD) signaling (JESD8-24 compliant)
I/O VDDQ = 1.1 V ± 50 mV or 1.2 V ± 50 mV
Core voltage
VDD = 1.3 V ±40 mV
On-die termination (ODT)
Programmable for clock, address/command, and data inputs
Internal self-calibration of output impedance through ZQ pin
Bus inversion to reduce switching noise and power
Programmable on/off for address and data
Address bus parity error protection
Training sequence for per-bit deskew
On-chip error correction code (ECC) to reduce soft error rate
JTAG 1149.1 test access port (JESD8-26 compliant)
1.3-V LVCMOS signaling
Available in 361-ball FCBGA Pb-free package (21 × 21 mm)
Selection Guide
Maximum operating frequency
Maximum operating current
CY7C4121KV13 – 8M ×18
CY7C4141KV13 – 4M ×36
Functional Description
The QDR™-IV HP (High-Performance) SRAM is a
high-performance memory device that has been optimized to
maximize the number of random transactions per second by the
use of two independent bidirectional data ports.
These ports are equipped with DDR interfaces and designated
as port A and port B respectively. Accesses to these two data
ports are concurrent and completely independent of each other.
Access to each port is through a common address bus running
at DDR. The control signals are running at SDR and determine
if a read or write should be performed.
There are three types of differential clocks:
(CK, CK#) for address and command clocking
(DKA, DKA#, DKB, DKB#) for data input clocking
(QKA, QKA#, QKB, QKB#) for data output clocking
Addresses for port A are latched on the rising edge of the input
clock (CK), and addresses for port B are latched on the falling
edge of the input clock (CK).
The QDR-IV HP SRAM device is offered in a two-word burst
option and is available in ×18 and ×36 bus width configurations.
For a ×18 bus width configuration, there are 22 address bits, and
for a ×36 bus width configuration, there are 21 address bits
An on-chip ECC circuitry detects and corrects all single-bit
memory errors, including those induced by soft-error events,
such as cosmic rays and alpha particles. The resulting SER of
these devices is expected to be less than 0.01 FITs/Mb, a
four-order-of-magnitude improvement over previous generation
For a complete list of related resources, click here.
1334 (MT/s)
×18 2500
×36 3200
1266 (MT/s)
1200 (MT/s)
1. Random Transaction Rate (RTR) is defined as the number of fully random memory accesses (reads or writes) that can be performed on the memory. RTR is measured
in million transactions per second.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-79343 Rev. *P
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 29, 2016

Cypress Semiconductor CY7C4141KV13
Logic Block Diagram – CY7C4121KV13
Document Number: 001-79343 Rev. *P
Page 2 of 45

Cypress Semiconductor CY7C4141KV13
Logic Block Diagram – CY7C4141KV13
Document Number: 001-79343 Rev. *P
Page 3 of 45

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