Pipelined SRAM. CY7C1350G Datasheet

CY7C1350G SRAM. Datasheet pdf. Equivalent

CY7C1350G Datasheet
Recommendation CY7C1350G Datasheet
Part CY7C1350G
Description 4-Mbit (128K x 36) Pipelined SRAM
Feature CY7C1350G; CY7C1350G 4-Mbit (128K × 36) Pipelined SRAM with NoBL™ Architecture 4-Mbit (128K × 36) Pipelined SR.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C1350G Datasheet




Cypress Semiconductor CY7C1350G
CY7C1350G
4-Mbit (128K × 36) Pipelined SRAM
with NoBL™ Architecture
4-Mbit (128K × 36) Pipelined SRAM with NoBL™ Architecture
Features
Pin compatible and functionally equivalent to ZBT™ devices
Internally self-timed output buffer control to eliminate the need
to use OE
Byte write capability
128K × 36 common I/O architecture
3.3 V power supply (VDD)
2.5 V/3.3 V I/O power supply (VDDQ)
Fast clock-to-output times
2.8 ns (for 200-MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
Asynchronous output enable (OE)
Available in Pb-free 100-pin TQFP package, Pb-free and
non Pb-free 119-ball BGA package
Burst capability – linear or interleaved burst order
“ZZ” sleep mode option
Logic Block Diagram
Functional Description
The CY7C1350G is a 3.3 V, 128K × 36 synchronous-pipelined
burst SRAM designed specifically to support unlimited true
back-to-back read/write operations without the insertion of wait
states. The CY7C1350G is equipped with the advanced No Bus
Latency™ (NoBL™) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of the
SRAM, especially in systems that require frequent write/read
transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which, when
deasserted, suspends operation and extends the previous clock
cycle. Maximum access delay from the clock rise is 2.8 ns
(200-MHz device).
Write operations are controlled by the four byte write select
(BW[A:D]) and a write enable (WE) input. All writes are conducted
with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
For a complete list of related documentation, click here.
A0, A1, A
MODE
CLK C
CEN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BWA
BWB
BWC
BWD
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
D
A
T
A
S
T
E
E
R
I
N
O
U
T
P
U
T
B
U
F
F
E
R
S
E
G
DQs
DQPA
DQPB
DQPC
DQPD
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
OE
CE1 READ LOGIC
CE2
CE3
ZZ SLEEP
CONTROL
Errata: For information on silicon errata, see "Errata" on page 19. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05524 Rev. *Q
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 7, 2016



Cypress Semiconductor CY7C1350G
CY7C1350G
Contents
Selection Guide ................................................................ 3
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Burst Read Accesses .................................................. 6
Single Write Accesses ................................................. 6
Burst Write Accesses .................................................. 6
Sleep Mode ................................................................. 6
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Partial Truth Table for Read/Write .................................. 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Electrical Characteristics ............................................... 10
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
AC Test Loads and Waveforms ..................................... 11
Switching Characteristics .............................................. 12
Switching Waveforms .................................................... 13
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagrams .......................................................... 16
Acronyms ........................................................................ 18
Document Conventions ................................................. 18
Units of Measure ....................................................... 18
Errata ............................................................................... 19
Part Numbers Affected .............................................. 19
Product Status ........................................................... 19
Ram9 NoBL ZZ Pin Issues Errata Summary ............. 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC®Solutions ....................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
Document Number: 38-05524 Rev. *Q
Page 2 of 22



Cypress Semiconductor CY7C1350G
CY7C1350G
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout [1]
200 MHz
2.8
265
40
133 MHz
4.0
225
40
Unit
ns
mA
mA
BYTE C
BYTE D
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1350G
80 DQPB
79 DQB
78 DQB
77 VDDQ
76 VSS
75
DQB
BYTE B
74 DQB
73 DQB
72 DQB
71 VSS
70 VDDQ
69 DQB
68 DQB
67 VSS
66 NC
65 VDD
64 ZZ
63 DQA
62 DQA
61 VDDQ
60 VSS
59 DQA
58
DQA
BYTE A
57 DQA
56 DQA
55 VSS
54 VDDQ
53 DQA
52 DQA
51 DQPA
Note
1. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see "Errata" on page 19.
Document Number: 38-05524 Rev. *Q
Page 3 of 22







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