CY7C1353G

CY7C1353G 4-Mbit (256K × 18) Flow-Through SRAM with NoBL™ Architecture 4-Mbit (256K × 18) Flow-Through SRAM with NoBL™ Architecture Features ■ Supports up to 100-MHz bus operations with zero wait states ❐ Data is transferred on every clock ■ Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self timed output buffer control to eliminate the need to use OE ■ Registered inputs for flow-through operation ■ Byte write capability ■ 256K × 18 common I/O architecture ■ 2.5 V/3.3 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 8.0 ns (for 100-MHz device) ■ Clock enable (CEN) pin to suspend operation ■ Synchronous self timed writes ■ Asynchronous output enable ■ Available in Pb-free 100-pin TQFP package ■ Burst capability – linear or interleaved burst order ■ Low standby power Logic Block Diagram Functional Description The CY7C1353G is a 3.3 V, 256K × 18 synchronous flow-through burst SRAM designed specifically to suppo...