Flow-Through SRAM. CY7C1353G Datasheet

CY7C1353G SRAM. Datasheet pdf. Equivalent

CY7C1353G Datasheet
Recommendation CY7C1353G Datasheet
Part CY7C1353G
Description 4-Mbit (256K x 18) Flow-Through SRAM
Feature CY7C1353G; CY7C1353G 4-Mbit (256K × 18) Flow-Through SRAM with NoBL™ Architecture 4-Mbit (256K × 18) Flow-Thro.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C1353G Datasheet




Cypress Semiconductor CY7C1353G
CY7C1353G
4-Mbit (256K × 18) Flow-Through SRAM
with NoBL™ Architecture
4-Mbit (256K × 18) Flow-Through SRAM with NoBL™ Architecture
Features
Supports up to 100-MHz bus operations with zero wait states
Data is transferred on every clock
Pin compatible and functionally equivalent to ZBT™ devices
Internally self timed output buffer control to eliminate the need
to use OE
Registered inputs for flow-through operation
Byte write capability
256K × 18 common I/O architecture
2.5 V/3.3 V I/O power supply (VDDQ)
Fast clock-to-output times
8.0 ns (for 100-MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self timed writes
Asynchronous output enable
Available in Pb-free 100-pin TQFP package
Burst capability – linear or interleaved burst order
Low standby power
Logic Block Diagram
Functional Description
The CY7C1353G is a 3.3 V, 256K × 18 synchronous
flow-through burst SRAM designed specifically to support
unlimited true back-to-back read/write operations without the
insertion of wait states. The CY7C1353G is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to enable
consecutive read/write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of data through the SRAM, especially in systems that
require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 8.0 ns (100-MHz device).
Write operations are controlled by the two byte write select
(BW[A:B]) and a write enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
For a complete list of related documentation, click here.
A0, A1, A
MODE
CLK C
CEN
CE
ADV/LD
BWA
BWB
WE
ADDRESS
REGISTER
A1
A0
D1
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
Q1
Q0
A1'
A0'
BURST
LOGIC
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
NE
G
DQs
DQPA
DQPB
OE
CE1 READ LOGIC
CE2
CE3
ZZ SLEEP
CONTROL
INPUT E
REGISTER
Errata: For information on silicon errata, see "Errata" on page 16. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05515 Rev. *P
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 7, 2016



Cypress Semiconductor CY7C1353G
CY7C1353G
Contents
Selection Guide ................................................................ 3
Pin Configuration ............................................................. 3
Pin Definitions .................................................................. 4
Functional Overview ........................................................ 5
Single Read Accesses ................................................ 5
Burst Read Accesses .................................................. 5
Single Write Accesses ................................................. 5
Burst Write Accesses .................................................. 6
Sleep Mode ................................................................. 6
Linear Burst Address Table ......................................... 6
Interleaved Burst Address Table ................................. 6
ZZ Mode Electrical Characteristics .............................. 6
Truth Table ........................................................................ 7
Partial Truth Table for Read/Write .................................. 7
Maximum Ratings ............................................................. 8
Operating Range ............................................................... 8
Electrical Characteristics ................................................. 8
Capacitance ...................................................................... 9
Thermal Resistance .......................................................... 9
AC Test Loads and Waveforms ....................................... 9
Switching Characteristics .............................................. 10
Switching Waveforms .................................................... 11
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagram ............................................................ 14
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Errata ............................................................................... 16
Part Numbers Affected .............................................. 16
Product Status ........................................................... 16
Ram9 NoBL ZZ Pin Issues Errata Summary ............. 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC®Solutions ....................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Document Number: 38-05515 Rev. *P
Page 2 of 19



Cypress Semiconductor CY7C1353G
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Pin Configuration
Description
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout [1]
CY7C1353G
100 MHz
8.0
205
40
Unit
ns
mA
mA
BYTE B
NC
NC
NC
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1353G
80 A
79 NC
78 NC
77 VDDQ
76 VSS
75 NC
74 DQPA
73 DQA
72 DQA
71 VSS
70 VDDQ
69 DQA
68 DQA
67 VSS
66 NC
65 VDD
64 ZZ
BYTE A
63 DQA
62 DQA
61 VDDQ
60 VSS
59 DQA
58 DQA
57 NC
56 NC
55 VSS
54 VDDQ
53 NC
52 NC
51 NC
Note
1. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see "Errata" on page 16.
Document Number: 38-05515 Rev. *P
Page 3 of 19







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