Flow-Through SRAM. CY7C1463BV33 Datasheet

CY7C1463BV33 SRAM. Datasheet pdf. Equivalent

CY7C1463BV33 Datasheet
Recommendation CY7C1463BV33 Datasheet
Part CY7C1463BV33
Description 36-Mbit (2 M x 18) Flow-Through SRAM
Feature CY7C1463BV33; CY7C1463BV33 36-Mbit (2 M × 18) Flow-Through SRAM with NoBL™ Architecture 36-Mbit (2 M × 18) Flow-T.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C1463BV33 Datasheet




Cypress Semiconductor CY7C1463BV33
CY7C1463BV33
36-Mbit (2 M × 18) Flow-Through SRAM with
NoBL™ Architecture
36-Mbit (2 M × 18) Flow-Through SRAM with NoBL™ Architecture
Features
No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
Supports up to 133-MHz bus operations with zero wait states
Data is transferred on every clock
Pin-compatible and functionally equivalent to ZBT™ devices
Internally self timed output buffer control to eliminate the need
to use OE
Registered inputs for flow through operation
Byte Write capability
3.3 V/2.5 V I/O power supply
Fast clock-to-output times
6.5 ns (for 133-MHz device)
Clock Enable (CEN) pin to enable clock and suspend operation
Synchronous self timed writes
Asynchronous Output Enable
CY7C1463BV33 available in JEDEC-standard Pb-free 100-pin
TQFP package
Three chip enables for simple depth expansion
Automatic Power down feature available using ZZ mode or CE
deselect
Burst Capability — linear or interleaved burst order
Low standby power
Functional Description
The CY7C1463BV33 is a 3.3 V, 2 M × 18 Synchronous Flow
-through Burst SRAM designed specifically to support unlimited
true back-to-back Read/Write operations without the insertion of
wait states. The CY7C1463BV33 is equipped with the advanced No
Bus Latency (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
through the SRAM, especially in systems that require frequent
Write-Read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Description
133 MHz
6.5
310
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-75212 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 5, 2016



Cypress Semiconductor CY7C1463BV33
CY7C1463BV33
Logic Block Diagram – CY7C1463BV33
A0, A1, A
MODE
CLK C
CEN
CE
ADV/LD
BW A
BW B
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER
A1
A0
D1
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
BURST
LOGIC
Q1
Q0
A1'
A0'
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
READ LOGIC
SLEEP
CONTROL
INPUT E
REGISTER
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
NE
G
DQs
DQP A
DQP B
Document Number: 001-75212 Rev. *C
Page 2 of 19



Cypress Semiconductor CY7C1463BV33
CY7C1463BV33
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Burst Read Accesses .................................................. 6
Single Write Accesses ................................................. 6
Burst Write Accesses .................................................. 7
Sleep Mode ................................................................. 7
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Truth Table for Read/Write .............................................. 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
Neutron Soft Error Immunity ........................................... 9
Electrical Characteristics ................................................. 9
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
AC Test Loads and Waveforms ..................................... 10
Switching Characteristics .............................................. 11
Switching Waveforms .................................................... 12
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagram ............................................................ 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Document Number: 001-75212 Rev. *C
Page 3 of 19







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