18-Mbit DDR II SIO SRAM Two-Word Burst Architecture
Description
CY7C1392KV18 CY7C1393KV18
18-Mbit DDR II SIO SRAM Two-Word Burst Architecture
18-Mbit DDR II SIO SRAM Two-Word Burst Architecture
Features
■ 18-Mbit density (2M × 8, 1M × 18) ■ 333-MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at
666 MHz) at 333 MHz ■ Two input clocks (...
