Burst Architecture. CY7C1393KV18 Datasheet

CY7C1393KV18 Architecture. Datasheet pdf. Equivalent

CY7C1393KV18 Datasheet
Recommendation CY7C1393KV18 Datasheet
Part CY7C1393KV18
Description 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture
Feature CY7C1393KV18; CY7C1392KV18 CY7C1393KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 18-Mbit DDR II SIO SR.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C1393KV18 Datasheet




Cypress Semiconductor CY7C1393KV18
CY7C1392KV18
CY7C1393KV18
18-Mbit DDR II SIO SRAM
Two-Word Burst Architecture
18-Mbit DDR II SIO SRAM Two-Word Burst Architecture
Features
18-Mbit density (2M × 8, 1M × 18)
333-MHz clock for high bandwidth
Two-word burst for reducing address bus frequency
Double data rate (DDR) interfaces (data transferred at
666 MHz) at 333 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Synchronous internally self timed writes
DDR II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to DDR I device with one cycle read latency
when DOFF is asserted LOW
1.8 V core power supply with HSTL inputs and outputs
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4 V–VDD)
Supports both 1.5 V and 1.8 V I/O supply
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Phase locked loop (PLL) for accurate data placement
Configurations
CY7C1392KV18 – 2M × 8
CY7C1393KV18 – 1M × 18
Functional Description
The CY7C1392KV18 and CY7C1393KV18 are 1.8 V
Synchronous Pipelined SRAMs, equipped with DDR II SIO
(double data rate separate I/O) architecture. The DDR II SIO
consists of two separate ports: the read port and the write port to
access the memory array. The read port has data outputs to
support read operations and the write port has data inputs to
support write operations. The DDR II SIO has separate data
inputs and data outputs to completely eliminate the need to
‘turnaround’ the data bus required with common I/O devices.
Access to each port is accomplished through a common address
bus. Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of C and C if provided, or on the rising edge of K and K if C/C are
not provided. Each address location is associated with two 8-bit
words in the case of CY7C1392KV18 and two 18-bit words in the
case of CY7C1393KV18 that burst sequentially into or out of the
device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need to capture
data separately from each individual DDR II SIO SRAM in the
system design. Output data clocks (C/C) enable maximum
system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum operating frequency
Maximum operating current
Description
333 MHz 300 MHz 250 MHz
333 300 250
× 8 Not Offered Not Offered 370
× 18 450 430 380
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-58907 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 19, 2016



Cypress Semiconductor CY7C1393KV18
CY7C1392KV18
CY7C1393KV18
Logic Block Diagram – CY7C1392KV18
D[7:0]
8
A(19:0) 20
Address
Register
Write
Data Reg
Write
Data Reg
K
K
DOFF
CLK
Gen.
R/W
VREF
LD
NWS[1:0]
Control
Logic
Read Data Reg.
16
8
8
Control
Logic
Reg.
Reg.
Reg. 8
8
LD
R/W
C
C
8
CQ
CQ
Q[7:0]
Logic Block Diagram – CY7C1393KV18
D[17:0]
18
A(18:0) 19
Address
Register
Write
Data Reg
Write
Data Reg
K
K
DOFF
CLK
Gen.
R/W
VREF
LD
BWS[1:0]
Control
Logic
Read Data Reg.
36
18
18
Control
Logic
Reg.
Reg.
Reg. 18
18
LD
R/W
C
C
18
CQ
CQ
Q[17:0]
Document Number: 001-58907 Rev. *G
Page 2 of 31



Cypress Semiconductor CY7C1393KV18
CY7C1392KV18
CY7C1393KV18
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 7
Read Operations ......................................................... 7
Write Operations ......................................................... 8
Byte Write Operations ................................................. 8
Single Clock Mode ...................................................... 8
DDR Operation ............................................................ 8
Depth Expansion ......................................................... 8
Programmable Impedance .......................................... 8
Echo Clocks ................................................................ 8
PLL .............................................................................. 8
Application Example ........................................................ 9
Truth Table ...................................................................... 10
Write Cycle Descriptions ............................................... 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port ....................................................... 11
Performing a TAP Reset ........................................... 11
TAP Registers ........................................................... 11
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Electrical Characteristics ...................................... 14
TAP AC Switching Characteristics ............................... 15
TAP Timing and Test Conditions .................................. 16
Identification Register Definitions ................................ 17
Scan Register Sizes ....................................................... 17
Instruction Codes ........................................................... 17
Boundary Scan Order .................................................... 18
Power Up Sequence in DDR II SRAM ........................... 19
Power Up Sequence ................................................. 19
PLL Constraints ......................................................... 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
Neutron Soft Error Immunity ......................................... 20
Electrical Characteristics ............................................... 20
DC Electrical Characteristics ..................................... 20
AC Electrical Characteristics ..................................... 22
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
AC Test Loads and Waveforms ..................................... 22
Switching Characteristics .............................................. 23
Switching Waveforms .................................................... 25
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagram ............................................................ 27
Acronyms ........................................................................ 28
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 31
Worldwide Sales and Design Support ....................... 31
Products .................................................................... 31
PSoC® Solutions ...................................................... 31
Cypress Developer Community ................................. 31
Technical Support ..................................................... 31
Document Number: 001-58907 Rev. *G
Page 3 of 31







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