Sync SRAM. CY7C1440KV25 Datasheet

CY7C1440KV25 SRAM. Datasheet pdf. Equivalent

CY7C1440KV25 Datasheet
Recommendation CY7C1440KV25 Datasheet
Part CY7C1440KV25
Description 36-Mbit (1M x 36) Pipelined Sync SRAM
Feature CY7C1440KV25; CY7C1440KV25 36-Mbit (1M × 36) Pipelined Sync SRAM 36-Mbit (1M × 36) Pipelined Sync SRAM Features ■.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C1440KV25 Datasheet




Cypress Semiconductor CY7C1440KV25
CY7C1440KV25
36-Mbit (1M × 36) Pipelined Sync SRAM
36-Mbit (1M × 36) Pipelined Sync SRAM
Features
Supports bus operation up to 250 MHz
Available speed grade is 250 MHz
Registered inputs and outputs for pipelined operation
2.5-V core power supply
2.5-V I/O power supply
Fast clock-to-output times
2.5 ns (for 250-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting interleaved or linear
burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Single-cycle Chip Deselect
CY7C1440KV25 available in Pb-free 165-ball FBGA package.
IEEE 1149.1 JTAG-Compatible Boundary Scan
“ZZ” Sleep Mode Option
Functional Description
The CY7C1440KV25 SRAM integrates 1M × 36 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE1), depth-expansion
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BWX, and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one, two or four bytes wide as
controlled by the byte write control inputs. GW when active LOW
causes all bytes to be written.
The CY7C1440KV25 operates from a +2.5 V core power supply
while all outputs may operate with a +2.5 V supply. All inputs
and outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
Maximum access time
Maximum operating current
Description
× 36
250 MHz
2.5
240
Unit
ns
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-94719 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 30, 2016



Cypress Semiconductor CY7C1440KV25
CY7C1440KV25
Logic Block Diagram – CY7C1440KV25
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BWD
BWC
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ADDRESS
REGISTER
2 A[1:0]
Q1
BURST
COUNTER
CLR AND Q0
LOGIC
DQD ,DQPD
BYTE
WRITE REGISTER
DQC ,DQPC
BYTE
WRITE REGISTER
DQB ,DQPB
BYTE
WRITE REGISTER
DQA ,DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
ZZ SLEEP
CONTROL
DQD ,DQPD
BYTE
WRITE DRIVER
DQC ,DQPC
BYTE
WRITE DRIVER
DQB ,DQPB
BYTE
WRITE DRIVER
DQA ,DQPA
BYTE
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQPA
DQPB
DQPC
DQPD
INPUT
REGISTERS
Document Number: 001-94719 Rev. *D
Page 2 of 30



Cypress Semiconductor CY7C1440KV25
CY7C1440KV25
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Single Write Accesses Initiated by ADSP ................... 6
Single Write Accesses Initiated by ADSC ................... 7
Burst Sequences ......................................................... 7
Sleep Mode ................................................................. 7
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Truth Table for Read/Write .............................................. 9
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 10
Disabling the JTAG Feature ...................................... 10
Test Access Port (TAP) ............................................. 10
PERFORMING A TAP RESET .................................. 10
TAP REGISTERS ...................................................... 10
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 12
TAP Controller Block Diagram ...................................... 13
TAP Timing ...................................................................... 13
TAP AC Switching Characteristics ............................... 14
2.5 V TAP AC Test Conditions ....................................... 15
2.5 V TAP AC Output Load Equivalent ......................... 15
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 15
Identification Register Definitions ................................ 16
Scan Register Sizes ....................................................... 16
Instruction Codes ........................................................... 16
Boundary Scan Order .................................................... 17
Maximum Ratings ........................................................... 18
Operating Range ............................................................. 18
Neutron Soft Error Immunity ......................................... 18
Electrical Characteristics ............................................... 18
DC Electrical Characteristics ..................................... 18
Capacitance .................................................................... 19
Thermal Resistance ........................................................ 19
AC Test Loads and Waveforms ..................................... 20
Switching Characteristics .............................................. 21
Switching Waveforms .................................................... 22
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagram ............................................................ 27
Acronyms ........................................................................ 28
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 30
Worldwide Sales and Design Support ....................... 30
Products .................................................................... 30
PSoC®Solutions ....................................................... 30
Cypress Developer Community ................................. 30
Technical Support ..................................................... 30
Document Number: 001-94719 Rev. *D
Page 3 of 30







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