CY7C1383KVE33

CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM (With ECC) 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM (With ECC) Features ■ Supports 133 MHz bus operations ■ 512K × 36 and 1M × 18 common I/O ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O supply (VDDQ) ■ Fast clock-to-output time ❐ 6.5 ns (133 MHz version) ■ Provides high performance 2-1-1-1 access rate ■ User selectable burst counter supporting interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed write ■ Asynchronous output enable ■ CY7C1381KV33/CY7C1381KVE33 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free 165-ball FBGA package. CY7C1383KV33/CY7C1383KVE33 available in JEDEC-standard Pb-free 100-pin TQFP. ■ IEEE 1149.1 JTAG-Compatible Boundary Scan ■ ZZ sleep mode option. ■ On-chip error correction code (ECC) to reduce soft error rate (SER) Functional D...