Sync SRAM. CY7C1387KV33 Datasheet

CY7C1387KV33 SRAM. Datasheet pdf. Equivalent

CY7C1387KV33 Datasheet
Recommendation CY7C1387KV33 Datasheet
Part CY7C1387KV33
Description 18-Mbit Pipelined DCD Sync SRAM
Feature CY7C1387KV33; CY7C1386KV33 CY7C1387KV33 18-Mbit (512K × 36/1M × 18) Pipelined DCD Sync SRAM 18-Mbit (512K × 36/1M.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C1387KV33 Datasheet




Cypress Semiconductor CY7C1387KV33
CY7C1386KV33
CY7C1387KV33
18-Mbit (512K × 36/1M × 18)
Pipelined DCD Sync SRAM
18-Mbit (512K × 36/1M × 18) Pipelined DCD Sync SRAM
Features
Supports bus operation up to 200 MHz
Available speed grades are 200, and 167 MHz
Registered inputs and outputs for pipelined operation
Optimal for performance (double-cycle deselect)
Depth expansion without wait state
3.3 V core power supply (VDD)
2.5 V or 3.3 V I/O power supply (VDDQ)
Fast clock-to-output times
3 ns (for 200 MHz device)
Provides high performance 3-1-1-1 access rate
User selectable burst counter supporting interleaved or linear
burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
CY7C1386KV33 available in JEDEC-standard Pb-free 100-pin
TQFP. CY7C1387KV33 available in JEDEC-standard Pb-free
100-pin TQFP
ZZ sleep mode option
Functional Description
The CY7C1386KV33/CY7C1387KV33 SRAM integrates
512K × 36/1M × 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive edge triggered clock input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining chip enable (CE1), depth expansion chip
enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and
ADV), write enables (BWX, and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and the ZZ
pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle.This part supports byte write
operations (see Pin Configurations on page 5 and Truth Table on
page 9 for further details). Write cycles can be one to four bytes
wide as controlled by the byte write control inputs. GW active
LOW causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off the
output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penalizing
system performance.
The CY7C1386KV33/CY7C1387KV33 operates from a +3.3 V
core power supply while all outputs operate with a +3.3 V or
+2.5 V supply. All inputs and outputs are JEDEC-standard and
JESD8-5-compatible.
Selection Guide
Maximum access time
Maximum operating current
Description
200 MHz 167 MHz Unit
3.0 3.4 ns
× 18 158
× 36 178
143
mA
163
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-97893 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 1, 2016



Cypress Semiconductor CY7C1387KV33
CY7C1386KV33
CY7C1387KV33
Logic Block Diagram – CY7C1386KV33
A0,A1,A
MODE
ADV
CLK
ADSC
ADSP
BW D
BW C
BW B
BW A
BWE
GW
CE 1
CE 2
CE 3
OE
ADDRESS
REGISTER
2 A[1:0]
BURST Q1
COUNTER AND
LOGIC
CLR Q0
DQ D,DQP D
BYTE
WRITE REGISTER
DQ c,DQP C
BYTE
WRITE REGISTER
DQ B,DQP B
BYTE
WRITE REGISTER
DQ A,DQP A
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
DQ D,DQP D
BYTE
WRITE DRIVER
DQ c,DQP C
BYTE
WRITE DRIVER
DQ B,DQP B
BYTE
WRITE DRIVER
DQ A,DQP A
BYTE
WRITE DRIVER
ZZ CONTROL
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP A
DQP B
DQP C
DQP D
INPUT
REGISTERS
Document Number: 001-97893 Rev. *D
Page 2 of 23



Cypress Semiconductor CY7C1387KV33
CY7C1386KV33
CY7C1387KV33
Logic Block Diagram – CY7C1387KV33
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW B
BW A
BWE
CE 1
CE 2
CE 3
OE
ADDRESS
REGISTER
2 A[1:0]
Q1
BURST
COUNTER AND
CLR Q0
DQ B, DQP B
BYTE
WRITE REGISTER
DQ A , DQP
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
SLEEP
CONTROL
DQ B , DQP B
BYTE
DQ A, DQP A
BYTE
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQ s,
DQP A
DQP B
INPUT
REGISTERS
Document Number: 001-97893 Rev. *D
Page 3 of 23







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