Sync SRAM. CY7C1327G Datasheet

CY7C1327G SRAM. Datasheet pdf. Equivalent

CY7C1327G Datasheet
Recommendation CY7C1327G Datasheet
Part CY7C1327G
Description 4-Mbit Pipelined Sync SRAM
Feature CY7C1327G; CY7C1327G 4-Mbit (256K × 18) Pipelined Sync SRAM 4-Mbit (256K × 18) Pipelined Sync SRAM Features ■ .
Manufacture Cypress Semiconductor
Datasheet
Download CY7C1327G Datasheet




Cypress Semiconductor CY7C1327G
CY7C1327G
4-Mbit (256K × 18) Pipelined Sync SRAM
4-Mbit (256K × 18) Pipelined Sync SRAM
Features
Registered inputs and outputs for pipelined operation
256K × 18 common I/O Architecture
3.3 V core power supply (VDD)
2.5 V I/O power supply (VDDQ)
Fast clock-to-output times
3.5 ns (for 166-MHz device)
Provide high performance 3-1-1-1 access rate
User-selectable burst counter supporting IntelPentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Offered in Pb-free 100-pin TQFP package
“ZZ” sleep mode option
Functional Description
The CY7C1327G SRAM integrates 256K × 18 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE1), depth-expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW[A:B], and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports byte write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two bytes wide as controlled
by the byte write control inputs. GW when active LOW causes all
bytes to be written.
The CY7C1327G operates from a +3.3 V core power supply
while all outputs also operate with a +3.3 V or a +2.5 V supply.
All inputs and outputs are JEDEC-standard JESD8-5-
compatible.
For a complete list of related documentation, click here.
Logic Block
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW B
BW A
BWE
GW
CE 1
CE2
CE3
OE
ADDRESS
REGISTER
2 A[1:0]
BURST Q1
COUNTER AND
LOGIC
CLR Q0
DQ B,DQP B
WRITE REGISTER
DQ A, DQP A
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
DQ B,DQP B
WRITE DRIVER
DQ A, DQP A
WRITE DRIVER
MEMORY
ARRAY
SENSE OUTPUT
AMPS REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP A
DQP B
INPUT
REGISTERS
ZZ SLEEP
CONTROL
Errata: For information on silicon errata, see "Errata" on page 21. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05519 Rev. *Q
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 4, 2016



Cypress Semiconductor CY7C1327G
CY7C1327G
Contents
Selection Guide ................................................................ 3
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 4
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Single Write Accesses Initiated by ADSP ................... 6
Single Write Accesses Initiated by ADSC ................... 6
Burst Sequences ......................................................... 6
Sleep Mode ................................................................. 6
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Truth Table for Read/Write .............................................. 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Neutron Soft Error Immunity ......................................... 10
Electrical Characteristics ............................................... 10
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
AC Test Loads and Waveforms ..................................... 12
Switching Characteristics .............................................. 13
Switching Waveforms .................................................... 14
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagrams .......................................................... 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Errata ............................................................................... 21
Part Numbers Affected .............................................. 21
Product Status ........................................................... 21
Ram9 Sync ZZ Pin Issues Errata Summary .............. 21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 24
Worldwide Sales and Design Support ....................... 24
Products .................................................................... 24
PSoC®Solutions ....................................................... 24
Cypress Developer Community ................................. 24
Technical Support ..................................................... 24
Document Number: 38-05519 Rev. *Q
Page 2 of 24



Cypress Semiconductor CY7C1327G
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Pin Configurations
Description
Figure 1. 100-pin TQFP pinout [1]
CY7C1327G
166 MHz
3.5
240
40
133 MHz
4.0
225
40
Unit
ns
mA
mA
BYTE B
NC
NC
NC
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
VDDQDQB
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1327G
80 A
79 NC
78 NC
77 VDDQ
76 VSS
75 NC
74 DQPA
73 DQA
72 DQA
71 VSS
70 VDDQ
69 DQA
68 DQA
67
66
VSS
NC
BYTE A
65 VDD
64 ZZ
63 DQA
62 DQA
61 VDDQ
60 VSS
59 DQA
58 DQA
57 NC
56 NC
55 VSS
54 VDDQ
53 NC
52 NC
51 NC
Note
1. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see "Errata" on page 21.
Document Number: 38-05519 Rev. *Q
Page 3 of 24





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