Flow-Through SRAM. CY7C1441AV33 Datasheet

CY7C1441AV33 SRAM. Datasheet pdf. Equivalent

CY7C1441AV33 Datasheet
Recommendation CY7C1441AV33 Datasheet
Part CY7C1441AV33
Description 36-Mbit Flow-Through SRAM
Feature CY7C1441AV33; CY7C1441AV33 36-Mbit (1 M × 36) Flow-Through SRAM 36-Mbit (1 M × 36) Flow-Through SRAM Features ■ S.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C1441AV33 Datasheet





Cypress Semiconductor CY7C1441AV33
CY7C1441AV33
36-Mbit (1 M × 36) Flow-Through SRAM
36-Mbit (1 M × 36) Flow-Through SRAM
Features
Supports 133-MHz bus operations
1 M × 36 common I/O
3.3 V core power supply
2.5 V or 3.3 V I/O power supply
Fast clock-to-output times
6.5 ns (133-MHz version)
Provide high-performance 2-1-1-1 access rate
User-selectable burst counter supporting IntelPentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous output enable
CY7C1441AV33 available in JEDEC-standard Pb-free 100-pin
TQFP package, Pb-free 165-ball FBGA package.
IEEE 1149.1 JTAG-Compatible Boundary Scan
“ZZ” Sleep Mode option
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Description
Functional Description
The CY7C1441AV33 are 3.3 V, 1 M × 36 Synchronous
Flow-through SRAMs, respectively designed to interface with
high-speed microprocessors with minimum glue logic. Maximum
access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit
on-chip counter captures the first address in a burst and
increments the address automatically for the rest of the burst
access. All synchronous inputs are gated by registers controlled
by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE1), depth-expansion Chip
Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and
ADV), Write Enables (BWx, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the ZZ
pin.
The CY7C1441AV33 allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address Strobe
(ADSC) inputs. Address advancement is controlled by the
Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
The CY7C1441AV33 operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click here.
133 MHz
6.5
310
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05357 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 29, 2014



Cypress Semiconductor CY7C1441AV33
Logic Block Diagram – CY7C1441AV33
A 0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW D
BW C
BW B
BW A
BWE
GW
CE1
CE2
CE3
OE
ZZ
ADDRESS
REGISTER
A [1:0]
BURST Q1
COUNTER
AND LOGIC
CLR Q0
DQ D, DQP D
BYTE
WRITE REGISTER
DQ C, DQP C
BYTE
WRITE REGISTER
DQ B, DQP B
BYTE
WRITE REGISTER
DQ A, DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
SLEEP
CONTROL
CY7C1441AV33
DQ D, DQP D
BYTE
WRITE REGISTER
DQ C, DQP C
BYTE
WRITE REGISTER
DQ B, DQP B
BYTE
WRITE REGISTER
DQ A, DQP A
BYTE
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQ s
DQP A
DQP B
DQP C
DQP D
INPUT
REGISTERS
Document Number: 38-05357 Rev. *M
Page 2 of 34



Cypress Semiconductor CY7C1441AV33
CY7C1441AV33
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 7
Single Read Accesses ................................................ 7
Single Write Accesses Initiated by ADSP ................... 7
Single Write Accesses Initiated by ADSC ................... 7
Burst Sequences ......................................................... 8
Sleep Mode ................................................................. 8
Interleaved Burst Address Table ................................. 8
Linear Burst Address Table ......................................... 8
ZZ Mode Electrical Characteristics .............................. 8
Truth Table ........................................................................ 9
Truth Table for Read/Write ............................................ 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port (TAP) ............................................. 11
PERFORMING A TAP RESET .................................. 11
TAP REGISTERS ...................................................... 11
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Timing ...................................................................... 14
TAP AC Switching Characteristics ............................... 15
3.3 V TAP AC Test Conditions ....................................... 16
3.3 V TAP AC Output Load Equivalent ......................... 16
2.5 V TAP AC Test Conditions ....................................... 16
2.5 V TAP AC Output Load Equivalent ......................... 16
TAP DC Electrical Characteristics and Operating
Conditions ....................................................................... 16
Identification Register Definitions ................................ 17
Scan Register Sizes ....................................................... 17
Identification Codes ....................................................... 17
Boundary Scan Order .................................................... 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
Electrical Characteristics ............................................... 19
DC Electrical Characteristics ..................................... 19
Capacitance .................................................................... 20
Thermal Resistance ........................................................ 20
AC Test Loads and Waveforms ..................................... 21
Switching Characteristics .............................................. 22
Timing Diagrams ............................................................ 23
Ordering Information ...................................................... 27
Ordering Code Definitions ......................................... 27
Package Diagrams .......................................................... 28
Acronyms ........................................................................ 30
Document Conventions ................................................. 30
Units of Measure ....................................................... 30
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 34
Worldwide Sales and Design Support ....................... 34
Products .................................................................... 34
PSoC® Solutions ....................................................... 34
Cypress Developer Community ................................. 34
Technical Support ..................................................... 34
Document Number: 38-05357 Rev. *M
Page 3 of 34





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