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Flow-Through SRAM. CY7C1447AV33 Datasheet

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Flow-Through SRAM. CY7C1447AV33 Datasheet






CY7C1447AV33 SRAM. Datasheet pdf. Equivalent




CY7C1447AV33 SRAM. Datasheet pdf. Equivalent





Part

CY7C1447AV33

Description

36-Mbit Flow-Through SRAM

Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1447AV33 Datasheet


Cypress Semiconductor CY7C1447AV33

CY7C1447AV33; CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 3 6-Mbit (1M x 36/2M x 18/512K x 72) Flow -Through SRAM Features ■ Supports 13 3-MHz bus operations ■ 1M x 36/2M x 1 8/512K x 72 common IO ■ 3.3V core pow er supply ■ 2.5V or 3.3V IO power sup ply ■ Fast clock-to-output times ❐ 6.5 ns (133-MHz version) ■ Provide hi gh-performance 2-1-1-1 access rate ■ User-selectable burst counter supp.


Cypress Semiconductor CY7C1447AV33

orting Intel® Pentium® interleaved or linear burst sequences ■ Separate pro cessor and controller address strobes Synchronous self-timed write ■ Asy nchronous output enable ■ CY7C1441AV3 3, CY7C1443AV33 available in JEDEC-stan dard Pb-free 100-pin TQFP package, Pb-f ree and non-lead-free 165-ball FBGA pac kage. CY7C1447AV33 available in Pb-free and non-lead-free 209-ball .


Cypress Semiconductor CY7C1447AV33

FBGA package ■ IEEE 1149.1 JTAG-Compat ible Boundary Scan ■ “ZZ” Sleep M ode option Selection Guide Description Maximum Access Time Maximum Operating C urrent Maximum CMOS Standby Current Fu nctional Description The CY7C1441AV33/ .



Part

CY7C1447AV33

Description

36-Mbit Flow-Through SRAM

Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1447AV33 Datasheet




 CY7C1447AV33
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
36-Mbit (1M x 36/2M x 18/512K x 72)
Flow-Through SRAM
Features
Supports 133-MHz bus operations
1M x 36/2M x 18/512K x 72 common IO
3.3V core power supply
2.5V or 3.3V IO power supply
Fast clock-to-output times
6.5 ns (133-MHz version)
Provide high-performance 2-1-1-1 access rate
User-selectable burst counter supporting Intel® Pentium®
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous output enable
CY7C1441AV33, CY7C1443AV33 available in
JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and
non-lead-free 165-ball FBGA package. CY7C1447AV33
available in Pb-free and non-lead-free 209-ball FBGA package
IEEE 1149.1 JTAG-Compatible Boundary Scan
“ZZ” Sleep Mode option
Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Functional Description
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are
3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-through
SRAMs, respectively designed to interface with high-speed
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip
counter captures the first address in a burst and increments the
address automatically for the rest of the burst access. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
Chip Enable (CE1), depth-expansion Chip Enables (CE2 and
CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (BWx, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the ZZ
pin.
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 allows
either interleaved or linear burst sequences, selected by the
MODE input pin. A HIGH selects an interleaved burst sequence,
while a LOW selects a linear burst sequence. Burst accesses
can be initiated with the Processor Address Strobe (ADSP) or the
cache Controller Address Strobe (ADSC) inputs. Address
advancement is controlled by the Address Advancement (ADV)
input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33
operates from a +3.3V core power supply while all outputs may
operate with either a +2.5 or +3.3V supply. All inputs and outputs
are JEDEC-standard JESD8-5-compatible.
133 MHz
6.5
310
120
100 MHz
8.5
290
120
Unit
ns
mA
mA
Note
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05357 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 09, 2008
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 CY7C1447AV33
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Logic Block Diagram – CY7C1441AV33 (1M x 36)
A 0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW D
BW C
BW B
BW A
BWE
GW
CE1
CE2
CE3
OE
ADDRESS
REGISTER
A [1:0]
BURST Q1
COUNTER
AND LOGIC
CLR Q0
DQ D, DQP D
BYTE
WRITE REGISTER
DQ C, DQP C
BYTE
WRITE REGISTER
DQ B, DQP B
BYTE
WRITE REGISTER
DQ A, DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
DQ D, DQP D
BYTE
WRITE REGISTER
DQ C, DQP C
BYTE
WRITE REGISTER
DQ B, DQP B
BYTE
WRITE REGISTER
DQ A, DQP A
BYTE
WRITE REGISTER
ZZ
SLEEP
CONTROL
Logic Block Diagram – CY7C1443AV33 (2Mx 18)
A 0,A1,A
MODE
ADV
CLK
ADSC
ADSP
BW B
BW A
BWE
GW
CE 1
CE 2
CE 3
OE
ADDRESS
REGISTER
A[1:0]
BURST Q1
COUNTER AND
LOGIC
CLR Q0
DQ B,DQP B
WRITE REGISTER
DQ A,DQP A
WRITE REGISTER
ENABLE
REGISTER
DQ B,DQP B
WRITE DRIVER
DQ A,DQP A
WRITE DRIVER
MEMORY
ARRAY
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQ s
DQP A
DQP B
DQP C
DQP D
INPUT
REGISTERS
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQP A
DQP B
INPUT
REGISTERS
ZZ SLEEP
CONTROL
Document #: 38-05357 Rev. *G
Page 2 of 31
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 CY7C1447AV33
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Logic Block Diagram – CY7C1447AV33 (512K x 72)
A0, A1,A
MODE
ADV
CLK
ADSC
ADSP
BW H
BW G
BW F
BW E
BW D
BW C
BW B
BW A
BWE
GW
CE1
CE2
CE3
OE
ZZ
ADDRESS
REGISTER
A[1:0]
BURST Q1
COUNTER
AND LOGIC
CLR Q0
DQ H, DQPH
WRITE REGISTER
DQ F, DQPF
WRITE REGISTER
DQ F, DQPF
WRITE REGISTER
DQ E, DQPE
WRITE REGISTER
DQ D, DQPD
WRITE REGISTER
DQ C, DQPC
WRITE REGISTER
DQ B, DQPB
WRITE REGISTER
DQ A, DQPA
WRITE REGISTER
ENABLE
REGISTER
SLEEP
CONTROL
DQ H, DQPH
WRITE DRIVER
DQ G, DQPG
WRITE DRIVER
DQ F, DQPF
WRITE DRIVER
DBQYTEE, D“Qa”PE
WRITE DRIVER
DQ D, DQPD
WRITE DRIVER
DQ C, DQPC
WRITE DRIVER
DQ B, DQPB
WRITE DRIVER
DQ A, DQPA
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
INPUT
REGISTERS
DQs
DQP A
DQP B
DQP C
DQP D
DQP E
DQP F
DQP G
DQP H
Document #: 38-05357 Rev. *G
Page 3 of 31
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