Pipelined SRAM. CY7C1364V25 Datasheet

CY7C1364V25 SRAM. Datasheet pdf. Equivalent

CY7C1364V25 Datasheet
Recommendation CY7C1364V25 Datasheet
Part CY7C1364V25
Description 256K x 36/256K x 32/512K x 18 Pipelined SRAM
Feature CY7C1364V25; PRELIMINARY CY7C1360V25 CY7C1362V25 CY7C1364V25 256K x 36/256K x 32/512K x 18 Pipelined SRAM Feat.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C1364V25 Datasheet




Cypress Semiconductor CY7C1364V25
PRELIMINARY
CY7C1360V25
CY7C1362V25
CY7C1364V25
256K x 36/256K x 32/512K x 18 Pipelined SRAM
Features
• Supports 200-MHz bus
• Fully registered inputs and outputs for pipelined
operation
• Single 2.5V power supply
• Fast clock-to-output times
— 3.1 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device
— 5.0 ns (for 100-MHz device
• User-selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Available as a 100-pin TQFP or 119 BGA
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1360V25, CY7C1364V25 and CY7C1362V25 are
2.5V, 256K x 36, 256K x 32 and 512K x 18 synchronous-pipe-
lined cache SRAM, respectively. They are designed to support
zero wait state secondary cache with minimal glue logic.
Logic Block Diagram
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise is 3.1 ns (200-MHz
device).
The CY7C1360V25/CY7C1364V25/CY7C1362V25 supports
either the interleaved burst sequence used by the Intel Pen-
tium processor or a linear burst sequence used by processors
such as the PowerPC™. The burst sequence is selected
through the MODE pin. Accesses can be initiated by assert-
ing either the Processor Address Strobe (ADSP) or the Con-
troller Address Strobe (ADSC) at clock rise. Address advance-
ment through the burst sequence is controlled by the ADV
input. A 2-bit on-chip wraparound burst counter captures the
first address in a burst sequence and automatically increments
the address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Select
(BWa,b,c,d for 1360V25/1364V25 and BWa,b for 1362V25) in-
puts. A Global Write Enable (GW) overrides all byte write in-
puts and writes data to all four bytes. All writes are conducted
with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to provide prop-
er data during depth expansion, OE is masked during the first
clock of a read cycle when emerging from a deselected state.
CLK
AX
DQX
DPX
BWX
ADV
Ax
GW
CCEE12
CE3
BWE
BWx
MODE
ADSP
ADSC
ZZ
OE
CONTROL
and WRITE
LOGIC
1360V25
A[17:0]
DQa,b,c,d
DPa,b,c,d
BWa,b,c,d
1362V25
A[18:0]
DQa,b
DPa,b
BWa,b
1364V25
A[18:0]
DQa,b
NC
BWa,b
CE
DaDta-In
Q
REG.
256Kx36/
512Kx18
MEMORY
ARRAY
DQx
DPx
Intel and Pentium are registered trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 3, 1999



Cypress Semiconductor CY7C1364V25
Pin Configurations
PRELIMINARY
100-Pin TQFP
CY7C1360V25
CY7C1362V25
CY7C1364V25
NC,DQPc
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
VDD
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
NC,DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1360/1364
(256K X 36/256K x 32)
80 NC,DQPb NC 1
79 DQb
NC 2
78 DQb
NC 3
77
VDDQ
VDDQ
4
76
VSSQ
VSSQ
5
75 DQb
NC 6
74 DQb
NC 7
73 DQb
DQb
8
72 DQb
DQb
9
71
VSSQ
VSSQ
10
70
VDDQ
VDDQ
11
69 DQb
DQb
12
68 DQb
DQb
13
67 VSS
VDD
14
66 NC
VDD
15
65 VDD
NC 16
64 ZZ
VSS 17
63 DQa
DQb
18
62 DQa
DQb
19
61
VDDQ
VDDQ
20
60
VSSQ
VSSQ
21
59 DQa
DQb
22
58 DQa
DQb
23
57 DQa
DPb
24
56 DQa
NC 25
55
VSSQ
VSSQ
26
54
VDDQ
VDDQ
27
53 DQa
NC 28
52 DQa
NC 29
51 NC,DQPa NC 30
CY7C1362
(512K x 18)
80 A
79 NC
78 NC
77 VDDQ
76 VSSQ
75 NC
74 DPa
73 DQa
72 DQa
71 VSSQ
70 VDDQ
69 DQa
68 DQa
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDDQ
60 VSSQ
59 DQa
58 DQa
57 NC
56 NC
55 VSSQ
54 VDDQ
53 NC
52 NC
51 NC
2



Cypress Semiconductor CY7C1364V25
PRELIMINARY
CY7C1360V25
CY7C1362V25
CY7C1364V25
Pin Configurations (continued)
119-Ball BGA
CY7C1360/1364 (256K x 36/256K x 32)
1 234567
A VDDQ
A
A ADSP A
A VDDQ
B NC CE2
C NC
A
A ADSC A
A VDD A
A NC
A NC
D DQc NC,DQPc VSS
E DQc DQc VSS
F VDDQ DQc
VSS
NC
CE1
OE
VSS NC,DQPb DQb
VSS DQb DQb
VSS
DQb
VDDQ
G
DQc
DQc
BWc
ADV
BWb
DQb
DQb
H DQc
DQc
VSS
GW
VSS
DQb
DQb
J VDDQ VDD
NC
VDD
NC
VDD
VDDQ
K DQd DQd VSS CLK VSS DQa DQa
L DQd DQd
M VDDQ DQd
N DQd DQd
BWd
VSS
VSS
NC
BWE
A1
BWa
VSS
VSS
DQa
DQa
DQa
DQa
VDDQ
DQa
P DQd NC,DQPd VSS A0 VSS NC,DQPa DQa
R NC
A MODE VDD VDD
A
NC
T NC
NC
A
A
A NC ZZ
U VDDQ TMS
TDI
TCK
TDO
DNU
VDDQ
CY7C1362 (512K x 18)
123 4567
A VDDQ
A
A ADSP A
A VDDQ
B NC CE2
A ADSC A
A NC
C NC
A
A VDD A
A NC
D DQb NC VSS NC VSS DQPa NC
E
NC
DQb
VSS
CE1
VSS
NC
DQa
F VDDQ NC
VSS
OE
VSS
DQa
VDDQ
G
NC
DQb
BWb
ADV
VSS
NC
DQa
H DQb
NC
VSS
GW
VSS
DQd
NC
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K NC DQb VSS CLK VSS NC DQa
L DQb NC VSS NC BWa DQa NC
M VDDQ DQb
VSS
BWE
VSS
NC VDDQ
N DQb NC VSS A1 VSS DQa NC
P
NC
DQPb
VSS
A0
VSS NC DQa
R NC
T NC
A MODE Vdd VDD
A A NC A
A
A
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
DNU
VDDQ
3





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