Sync SRAM. CY7C1338G Datasheet

CY7C1338G SRAM. Datasheet pdf. Equivalent

CY7C1338G Datasheet
Recommendation CY7C1338G Datasheet
Part CY7C1338G
Description 4-Mbit Flow-Through Sync SRAM
Feature CY7C1338G; CY7C1338G 4-Mbit (128K × 32) Flow-Through Sync SRAM 4-Mbit (128K × 32) Flow-Through Sync SRAM Featu.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C1338G Datasheet





Cypress Semiconductor CY7C1338G
CY7C1338G
4-Mbit (128K × 32) Flow-Through
Sync SRAM
4-Mbit (128K × 32) Flow-Through Sync SRAM
Features
128K × 32 common I/O
3.3 V core power supply (VDD)
2.5 V or 3.3 V I/O supply (VDDQ)
Fast clock-to-output times
8.0 ns (100-MHz version)
Provide high-performance 2-1-1-1 access rate
User-selectable burst counter supporting IntelPentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous output enable
Offered in Pb-free 100-pin TQFP package
“ZZ” sleep mode option
Functional Description
The CY7C1338G is a 128K × 32 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
8.0 ns (100-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE1), depth-expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW[A:D], and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
The CY7C1338G allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs. Address advancement is controlled by the
address advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
The CY7C1338G operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click here.
Logic Block Diagram
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BWD
BWC
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ZZ
ADDRESS
REGISTER
A[1:0]
BURST Q1
COUNTER
AND LOGIC
CLR Q0
DQD BYTE
WRITE REGISTER
DQC BYTE
WRITE REGISTER
DQB BYTE
WRITE REGISTER
DQA BYTE
WRITE REGISTER
ENABLE
REGISTER
SLEEP
CONTROL
DQD BYTE
WRITE REGISTER
DQC BYTE
WRITE REGISTER
DQB BYTE
WRITE REGISTER
DQA BYTE
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
INPUT
REGISTERS
Errata: For information on silicon errata, see "Errata" on page 20. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05521 Rev. *P
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 8, 2016



Cypress Semiconductor CY7C1338G
CY7C1338G
Contents
Selection Guide ................................................................ 3
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 4
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Single Write Accesses Initiated by ADSP ................... 6
Single Write Accesses Initiated by ADSC ................... 6
Burst Sequences ......................................................... 6
Sleep Mode ................................................................. 6
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Partial Truth Table for Read/Write .................................. 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Electrical Characteristics ............................................... 10
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
AC Test Loads and Waveforms ..................................... 11
Switching Characteristics .............................................. 12
Timing Diagrams ............................................................ 13
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 17
Package Diagrams .......................................................... 18
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Errata ............................................................................... 20
Part Numbers Affected .............................................. 20
Product Status ........................................................... 20
Ram9 Sync ZZ Pin Issues Errata Summary .............. 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 23
Worldwide Sales and Design Support ....................... 23
Products .................................................................... 23
PSoC®Solutions ....................................................... 23
Cypress Developer Community ................................. 23
Technical Support ..................................................... 23
Document Number: 38-05521 Rev. *P
Page 2 of 23



Cypress Semiconductor CY7C1338G
Selection Guide
Maximum access time
Maximum operating current
Maximum standby current
Pin Configurations
Description
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout [1]
CY7C1338G
100 MHz
8.0
205
40
Unit
ns
mA
mA
BYTE C
BYTE D
NC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1338G
80 NC
79 DQB
78 DQB
77 VDDQ
76 VSSQ
75 DQB
74 DQB
73 DQB
72 DQB
71 VSSQ
70 VDDQ
69 DQB
68 DQB
67 VSS
66 NC
65 VDD
64 ZZ
63 DQA
62 DQA
61 VDDQ
60 VSSQ
59 DQA
58 DQA
57 DQA
56 DQA
55 VSSQ
54 VDDQ
53 DQA
52 DQA
51 NC
BYTE B
BYTE A
Note
1. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see "Errata" on page 20.
Document Number: 38-05521 Rev. *P
Page 3 of 23





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