Sync SRAM. CY7C1329H Datasheet

CY7C1329H SRAM. Datasheet pdf. Equivalent

CY7C1329H Datasheet
Recommendation CY7C1329H Datasheet
Part CY7C1329H
Description 2-Mbit Pipelined Sync SRAM
Feature CY7C1329H; CY7C1329H 2-Mbit (64 K × 32) Pipelined Sync SRAM 2-Mbit (64 K × 32) Pipelined Sync SRAM Features ■ .
Manufacture Cypress Semiconductor
Datasheet
Download CY7C1329H Datasheet





Cypress Semiconductor CY7C1329H
CY7C1329H
2-Mbit (64 K × 32) Pipelined Sync SRAM
2-Mbit (64 K × 32) Pipelined Sync SRAM
Features
Registered inputs and outputs for pipelined operation
64 K × 32 common I/O architecture
3.3 V core power supply
2.5 V/3.3 V I/O operation
Fast clock-to-output times
4.0 ns (for 133-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting IntelPentium®
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous output enable
Offered in JEDEC-standard lead-free 100-pin TQFP package
“ZZ” Sleep Mode Option
Functional Description
The CY7C1329H SRAM integrates 64 K × 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE1), depth-expansion
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BW[A:D] and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. This part supports Byte Write
operations (see Pin Definitions on page 4 and Truth Table on
page 7 for further details). Write cycles can be one to four bytes
wide as controlled by the Byte Write control inputs. GW when
active LOW causes all bytes to be written.
The CY7C1329H operates from a +3.3 V core power supply
while all outputs operate with either a +2.5 V or +3.3 V supply.
All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click here.
Logic Block Diagram
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BWD
BWC
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ADDRESS
REGISTER
2 A[1:0]
Q1
BURST
COUNTER
CLR AND Q0
LOGIC
DQD
BYTE
WRITE REGISTER
DQC
BYTE
WRITE REGISTER
DQB
BYTE
WRITE REGISTER
DQA
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
DQD
BYTE
WRITE DRIVER
DQC
BYTE
WRITE DRIVER
DQB
BYTE
WRITE DRIVER
DQA
BYTE
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
INPUT
REGISTERS
ZZ SLEEP
CONTROL
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05673 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 20, 2014



Cypress Semiconductor CY7C1329H
CY7C1329H
Contents
Selection Guide ................................................................ 3
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 4
Functional Overview ........................................................ 5
Single Read Accesses ................................................ 5
Single Write Accesses Initiated by ADSP ................... 5
Single Write Accesses Initiated by ADSC ................... 5
Burst Sequences ......................................................... 5
Sleep Mode ................................................................. 5
Interleaved Burst Address Table ................................. 6
Linear Burst Address Table ......................................... 6
ZZ Mode Electrical Characteristics .............................. 6
Truth Table ........................................................................ 7
Truth Table for Read/Write .............................................. 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
Electrical Characteristics ................................................. 9
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
AC Test Loads and Waveforms ..................................... 10
Switching Characteristics .............................................. 11
Switching Waveforms .................................................... 12
Ordering Information ...................................................... 16
Ordering Code Definitions ......................................... 16
Package Diagram ............................................................ 17
Acronyms ........................................................................ 18
Document Conventions ................................................. 18
Units of Measure ....................................................... 18
Document History Page ................................................. 19
Sales, Solutions, and Legal Information ...................... 20
Worldwide Sales and Design Support ....................... 20
Products .................................................................... 20
PSoC® Solutions ...................................................... 20
Cypress Developer Community ................................. 20
Technical Support ..................................................... 20
Document Number: 38-05673 Rev. *H
Page 2 of 20



Cypress Semiconductor CY7C1329H
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Description
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
CY7C1329H
133 MHz
4.0
225
40
Unit
ns
mA
mA
BYTE C
BYTE D
NC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1329H
80 NC
79 DQB
78 DQB
77 VDDQ
76 VSSQ
75
74
DQB
DQB
BYTE B
73 DQB
72 DQB
71 VSSQ
70 VDDQ
69 DQB
68 DQB
67 VSS
66 NC
65 VDD
64 ZZ
63 DQA
62 DQA
61 VDDQ
60 VSSQ
59 DQA
58 DQA
57
DQA
BYTE A
56 DQA
55 VSSQ
54 VDDQ
53 DQA
52 DQA
51 NC
Document Number: 38-05673 Rev. *H
Page 3 of 20





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