Burst Architecture. CY7C1650KV18 Datasheet

CY7C1650KV18 Architecture. Datasheet pdf. Equivalent

CY7C1650KV18 Datasheet
Recommendation CY7C1650KV18 Datasheet
Part CY7C1650KV18
Description 144-Mbit DDR II+ SRAM Two-Word Burst Architecture
Feature CY7C1650KV18; CY7C1648KV18 CY7C1650KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency).
Manufacture Cypress Semiconductor
Datasheet
Download CY7C1650KV18 Datasheet





Cypress Semiconductor CY7C1650KV18
CY7C1648KV18
CY7C1650KV18
144-Mbit DDR II+ SRAM Two-Word
Burst Architecture (2.0 Cycle Read Latency)
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
Features
144-Mbit density (8 M × 18, 4 M × 36)
450-MHz clock for high bandwidth
Two-word burst for reducing address bus frequency
Double data rate (DDR) interfaces (data transferred at
900 MHz) at 450 MHz
Available in 2.0-clock cycle latency
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Data valid pin (QVLD) to indicate valid data on the output
Synchronous internally self-timed writes
DDR II+ operates with 2.0-cycle read latency when DOFF is
asserted high
Operates similar to DDR I device with one cycle read latency
when DOFF is asserted low
Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD[1]
Supports both 1.5 V and 1.8 V I/O supply
High-speed transceiver logic (HSTL) inputs and variable drive
HSTL output buffers
Available in 165-ball fine-pitch ball grid array (FBGA) package
(15 × 17 × 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Phase locked loop (PLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C1648KV18 – 8 M × 18
CY7C1650KV18 – 4 M × 36
Functional Description
The CY7C1648KV18, and CY7C1650KV18 are 1.8-V
synchronous pipelined SRAMs equipped with DDR II+
architecture. The DDR II+ consists of an SRAM core with
advanced synchronous peripheral circuitry. Addresses for read
and write are latched on alternate rising edges of the input (K)
clock. Write data is registered on the rising edges of both K and
K. Read data is driven on the rising edges of K and K. Each
address location is associated with two18-bit words
(CY7C1648KV18), or 36-bit words (CY7C1650KV18) that burst
sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum operating frequency
Maximum operating current
Description
450 MHz 400 MHz
450 400
× 18 Not Offered 730
× 36 980
900
Unit
MHz
mA
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4 V to VDD.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-44061 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 18, 2015



Cypress Semiconductor CY7C1650KV18
Logic Block Diagram – CY7C1648KV18
CY7C1648KV18
CY7C1650KV18
A(21:0)
22
LD
K
K
DOFF
VREF
R/W
BWS[1:0]
Address
Register
CLK
Gen.
Control
Logic
Write
Reg
Write
Reg
Read Data Reg.
36
18
18
18
Output
Logic
Control
R/W
Reg.
Reg.
Reg. 18
18
18
CQ
CQ
DQ[17:0]
QVLD
Logic Block Diagram – CY7C1650KV18
A(20:0)
21
LD
K
K
DOFF
VREF
R/W
BWS[3:0]
Address
Register
CLK
Gen.
Control
Logic
Write
Reg
Write
Reg
Read Data Reg.
72
36
36
36
Output
Logic
Control
R/W
Reg.
Reg.
Reg. 36
36
36
CQ
CQ
DQ[35:0]
QVLD
Document Number: 001-44061 Rev. *K
Page 2 of 29



Cypress Semiconductor CY7C1650KV18
CY7C1648KV18
CY7C1650KV18
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Read Operations ......................................................... 6
Write Operations ......................................................... 6
Byte Write Operations ................................................. 6
DDR Operation ............................................................ 6
Depth Expansion ......................................................... 7
Programmable Impedance .......................................... 7
Echo Clocks ................................................................ 7
Valid Data Indicator (QVLD) ........................................ 7
PLL .............................................................................. 7
Application Example ........................................................ 7
Truth Table ........................................................................ 8
Write Cycle Descriptions ................................................. 8
Write Cycle Descriptions ................................................. 9
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 10
Disabling the JTAG Feature ...................................... 10
Test Access Port ....................................................... 10
Performing a TAP Reset ........................................... 10
TAP Registers ........................................................... 10
TAP Instruction Set ................................................... 10
TAP Controller State Diagram ....................................... 12
TAP Controller Block Diagram ...................................... 13
TAP Electrical Characteristics ...................................... 13
TAP AC Switching Characteristics ............................... 14
TAP Timing and Test Conditions .................................. 15
Identification Register Definitions ................................ 16
Scan Register Sizes ....................................................... 16
Instruction Codes ........................................................... 16
Boundary Scan Order .................................................... 17
Power Up Sequence in DDR II+ SRAM ......................... 18
Power Up Sequence ................................................. 18
PLL Constraints ......................................................... 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
Neutron Soft Error Immunity ......................................... 19
Electrical Characteristics ............................................... 19
DC Electrical Characteristics ..................................... 19
AC Electrical Characteristics ..................................... 21
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
AC Test Loads and Waveforms ..................................... 21
Switching Characteristics .............................................. 22
Switching Waveforms .................................................... 23
Read/Write/Deselect Sequence ................................ 23
Ordering Information ...................................................... 24
Ordering Code Definitions ......................................... 24
Package Diagram ............................................................ 25
Acronyms ........................................................................ 26
Document Conventions ................................................. 26
Units of Measure ....................................................... 26
Document History Page ................................................. 27
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support ....................... 29
Products .................................................................... 29
PSoC® Solutions ...................................................... 29
Cypress Developer Community ................................. 29
Technical Support ..................................................... 29
Document Number: 001-44061 Rev. *K
Page 3 of 29





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