18-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1311KV18/CY7C1911KV18 CY7C1313KV18/CY7C1315KV18
18-Mbit QDR® II SRAM Four-Word Burst Architecture
18-Mbit QDR® II...
Description
CY7C1311KV18/CY7C1911KV18 CY7C1313KV18/CY7C1315KV18
18-Mbit QDR® II SRAM Four-Word Burst Architecture
18-Mbit QDR® II SRAM Four-Word Burst Architecture
Features
■ Separate independent read and write data ports ❐ Supports concurrent transactions
■ 333-MHz clock for high bandwidth ■ Four-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only ■ Two Input Clocks for Output Data (C and C) to minimize Clock
skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems ■ Single multiplexed address input bus latches address inputs
for read and write ports ■ Separate port selects for depth expansion ■ Synchronous internally self-timed writes ■ QDR® II operates with 1.5 cycle read latency when DOFF is
asserted HIGH ■ Operates similar to QDR I de...
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