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CY7C1312KV18 Dataheets PDF



Part Number CY7C1312KV18
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description 18-Mbit QDR II SRAM Two-Word Burst Architecture
Datasheet CY7C1312KV18 DatasheetCY7C1312KV18 Datasheet (PDF)

CY7C1312KV18/CY7C1314KV18 18-Mbit QDR® II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 333 MHz clock for high bandwidth ■ Two-word burst on all accesses ■ Double-data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for out.

  CY7C1312KV18   CY7C1312KV18


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