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Burst Architecture. CY7C1312KV18 Datasheet

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Burst Architecture. CY7C1312KV18 Datasheet






CY7C1312KV18 Architecture. Datasheet pdf. Equivalent




CY7C1312KV18 Architecture. Datasheet pdf. Equivalent





Part

CY7C1312KV18

Description

18-Mbit QDR II SRAM Two-Word Burst Architecture

Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1312KV18 Datasheet


Cypress Semiconductor CY7C1312KV18

CY7C1312KV18; CY7C1312KV18/CY7C1314KV18 18-Mbit QDR® II SRAM Two-Word Burst Architecture 18 -Mbit QDR® II SRAM Two-Word Burst Arch itecture Features ■ Separate independ ent read and write data ports ❐ Suppo rts concurrent transactions ■ 333 MHz clock for high bandwidth ■ Two-word burst on all accesses ■ Double-data r ate (DDR) interfaces on both read and w rite ports (data transferred a.


Cypress Semiconductor CY7C1312KV18

t 666 MHz) at 333 MHz ■ Two input cloc ks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two in put clocks for output data (C and C) to minimize clock skew and flight time mi smatches ■ Echo clocks (CQ and CQ) si mplify data capture in high-speed syste ms ■ Single multiplexed address input bus latches address inputs for both re ad and write ports ■ Separat.


Cypress Semiconductor CY7C1312KV18

e port selects for depth expansion ■ S ynchronous internally self-timed writes ■ QDR® II operates with 1.5 cycle r ead latency when DOFF is asserted HIGH ■ Operates similar to QDR I device wi th one cycle read latency when DOFF is asserted LOW ■ Available in × 18, an d × 36 configurations ■ Full data co herency, providing most current data Core VDD = 1.8 V (±0.1 V); I/O .



Part

CY7C1312KV18

Description

18-Mbit QDR II SRAM Two-Word Burst Architecture

Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1312KV18 Datasheet




 CY7C1312KV18
CY7C1312KV18/CY7C1314KV18
18-Mbit QDR® II SRAM
Two-Word Burst Architecture
18-Mbit QDR® II SRAM Two-Word Burst Architecture
Features
Separate independent read and write data ports
Supports concurrent transactions
333 MHz clock for high bandwidth
Two-word burst on all accesses
Double-data rate (DDR) interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Single multiplexed address input bus latches address inputs
for both read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
QDR® II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to QDR I device with one cycle read latency
when DOFF is asserted LOW
Available in × 18, and × 36 configurations
Full data coherency, providing most current data
Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD
Supports both 1.5 V and 1.8 V I/O supply
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
Offered in both Pb-free and non Pb-free packages
Variable drive HSTL output buffers
JTAG 1149.1 compatible test access port
PLL for accurate data placement
Configurations
CY7C1312KV18 – 1M × 18
CY7C1314KV18 – 512K × 36
Functional Description
The CY7C1312KV18, and CY7C1314KV18 are 1.8 V
Synchronous Pipelined SRAMs, equipped with QDR II
architecture. QDR II architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II architecture has separate data inputs and
data outputs to completely eliminate the need to ‘turnaround’ the
data bus that exists with common I/O devices. Access to each
port is through a common address bus. Addresses for read and
write addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the QDR II read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with two 18-bit
words (CY7C1312KV18), or 36-bit words (CY7C1314KV18) that
burst sequentially into or out of the device. Because data can be
transferred into and out of the device on every rising edge of both
input clocks (K and K and C and C), memory bandwidth is
maximized while simplifying system design by eliminating bus
turnarounds.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum operating frequency
Maximum operating current
Description
× 18
× 36
333 MHz
333
690
840
300 MHz
300
640
780
250 MHz
250
560
670
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-58903 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 28, 2017





 CY7C1312KV18
CY7C1312KV18/CY7C1314KV18
Logic Block Diagram – CY7C1312KV18
D[17:0]
18
A(18:0) 19
Address
Register
Write
Reg
Write
Reg
K
K
DOFF
VREF
WPS
BWS[1:0]
CLK
Gen.
Control
Logic
Read Data Reg.
36
18
18
Address
Register
19 A(18:0)
Control
Logic
RPS
C
C
Reg.
Reg.
Reg. 18
18
18
CQ
CQ
Q[17:0]
Logic Block Diagram – CY7C1314KV18
D[35:0]
36
A(17:0) 18
Address
Register
K
K
DOFF
VREF
WPS
BWS[3:0]
CLK
Gen.
Control
Logic
Write
Reg
Write
Reg
Read Data Reg.
72
36
36
Address
Register
18 A(17:0)
Control
Logic
RPS
C
C
Reg.
Reg.
Reg. 36
36
36
CQ
CQ
Q[35:0]
Document Number: 001-58903 Rev. *K
Page 2 of 31





 CY7C1312KV18
CY7C1312KV18/CY7C1314KV18
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Read Operations ......................................................... 6
Write Operations ......................................................... 6
Byte Write Operations ................................................. 7
Single Clock Mode ...................................................... 7
Concurrent Transactions ............................................. 7
Depth Expansion ......................................................... 7
Programmable Impedance .......................................... 7
Echo Clocks ................................................................ 7
PLL .............................................................................. 7
Application Example ........................................................ 8
Truth Table ........................................................................ 9
Write Cycle Descriptions ................................................. 9
Write Cycle Descriptions ............................................... 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port ....................................................... 11
Performing a TAP Reset ........................................... 11
TAP Registers ........................................................... 11
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Electrical Characteristics ...................................... 14
TAP AC Switching Characteristics ............................... 15
TAP Timing and Test Conditions .................................. 16
Identification Register Definitions ................................ 17
Scan Register Sizes ....................................................... 17
Instruction Codes ........................................................... 17
Boundary Scan Order .................................................... 18
Power Up Sequence in QDR II SRAM ........................... 19
Power Up Sequence ................................................. 19
PLL Constraints ......................................................... 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
Neutron Soft Error Immunity ......................................... 20
Electrical Characteristics ............................................... 20
DC Electrical Characteristics ..................................... 20
AC Electrical Characteristics ..................................... 22
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
AC Test Loads and Waveforms ..................................... 22
Switching Characteristics .............................................. 23
Switching Waveforms .................................................... 25
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagram ............................................................ 27
Acronyms ........................................................................ 28
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 31
Worldwide Sales and Design Support ....................... 31
Products .................................................................... 31
PSoC® Solutions ...................................................... 31
Cypress Developer Community ................................. 31
Technical Support ..................................................... 31
Document Number: 001-58903 Rev. *K
Page 3 of 31



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