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Burst Architecture. CY7C1412KV18 Datasheet

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Burst Architecture. CY7C1412KV18 Datasheet






CY7C1412KV18 Architecture. Datasheet pdf. Equivalent




CY7C1412KV18 Architecture. Datasheet pdf. Equivalent





Part

CY7C1412KV18

Description

36-Mbit QDR II SRAM Two-Word Burst Architecture



Feature


CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 3 6-Mbit QDR® II SRAM Two-Word Burst Arc hitecture 36-Mbit QDR® II SRAM Two-Wo rd Burst Architecture Features ■ Sepa rate independent read and write data po rts ❐ Supports concurrent transaction s ■ 333 MHz clock for high bandwidth ■ Two-word burst on all accesses ■ Double data rate (DDR) Interfaces on bo th read and write ports (data .
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1412KV18 Datasheet


Cypress Semiconductor CY7C1412KV18

CY7C1412KV18; transferred at 666 MHz) at 333 MHz ■ T wo input clocks (K and K) for precise D DR timing ❐ SRAM uses rising edges on ly ■ Two input clocks for output data (C and C) to minimize clock skew and f light time mismatches ■ Echo clocks ( CQ and CQ) simplify data capture in hig h speed systems ■ Single multiplexed address input bus latches address input s for both read and write po.


Cypress Semiconductor CY7C1412KV18

rts ■ Separate port selects for depth expansion ■ Synchronous internally se lf-timed writes ■ QDR® II operates w ith 1.5 cycle read latency when DOFF is asserted HIGH ■ Operates similar to QDR I device with 1 cycle read latency whe .


Cypress Semiconductor CY7C1412KV18

.

Part

CY7C1412KV18

Description

36-Mbit QDR II SRAM Two-Word Burst Architecture



Feature


CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 3 6-Mbit QDR® II SRAM Two-Word Burst Arc hitecture 36-Mbit QDR® II SRAM Two-Wo rd Burst Architecture Features ■ Sepa rate independent read and write data po rts ❐ Supports concurrent transaction s ■ 333 MHz clock for high bandwidth ■ Two-word burst on all accesses ■ Double data rate (DDR) Interfaces on bo th read and write ports (data .
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1412KV18 Datasheet




 CY7C1412KV18
CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
36-Mbit QDR® II SRAM Two-Word
Burst Architecture
36-Mbit QDR® II SRAM Two-Word Burst Architecture
Features
Separate independent read and write data ports
Supports concurrent transactions
333 MHz clock for high bandwidth
Two-word burst on all accesses
Double data rate (DDR) Interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Single multiplexed address input bus latches address inputs
for both read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
QDR® II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted LOW
Available in × 9, × 18, and × 36 configurations
Full data coherency, providing most current data
Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD
Supports both 1.5 V and 1.8 V I/O supply
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
Offered in both Pb-free and non Pb-free Packages
Variable drive HSTL output buffers
JTAG 1149.1 compatible test access port
Phase locked loop (PLL) for accurate data placement
Configurations
CY7C1425KV18 – 4M × 9
CY7C1412KV18 – 2M × 18
CY7C1414KV18 – 1M × 36
Functional Description
The CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18
are 1.8 V synchronous pipelined SRAMs, equipped with QDR II
architecture. QDR II architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II architecture has separate data inputs and
data outputs to completely eliminate the need to “turnaround” the
data bus that exists with common I/O devices. Access to each
port is through a common address bus. Addresses for read and
write addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the QDR II read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with two 9-bit
words (CY7C1425KV18), 18-bit words (CY7C1412KV18), or
36-bit words (CY7C1414KV18) that burst sequentially into or out
of the device. Because data can be transferred into and out of
the device on every rising edge of both input clocks (K and K and
C and C), memory bandwidth is maximized while simplifying
system design by eliminating bus turnarounds.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum operating frequency
Maximum operating current
Description
333 MHz 300 MHz 250 MHz Unit
333 300 250 MHz
× 9 730 680 590 mA
× 18 750 700 610
× 36 910 850 730
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-57825 Rev. *N
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 16, 2016




 CY7C1412KV18
CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
Logic Block Diagram – CY7C1425KV18
D[8:0]
9
A(20:0) 21
Address
Register
Write
Reg
Write
Reg
K
K
DOFF
VREF
WPS
BWS[0]
CLK
Gen.
Control
Logic
Read Data Reg.
18
9
9
Address
Register
21 A(20:0)
Control
Logic
RPS
C
C
Reg.
Reg.
Reg. 9
9
9
CQ
CQ
Q[8:0]
Logic Block Diagram – CY7C1412KV18
D[17:0]
18
A(19:0) 20
Address
Register
Write
Reg
Write
Reg
K
K
DOFF
VREF
WPS
BWS[1:0]
CLK
Gen.
Control
Logic
Read Data Reg.
36
18
18
Address
Register
20 A(19:0)
Control
Logic
RPS
C
C
Reg.
Reg.
Reg. 18
18
18
CQ
CQ
Q[17:0]
Document Number: 001-57825 Rev. *N
Page 2 of 33




 CY7C1412KV18
CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
Logic Block Diagram – CY7C1414KV18
D[35:0]
36
A(18:0) 19
Address
Register
K
K
DOFF
VREF
WPS
BWS[3:0]
CLK
Gen.
Control
Logic
Write
Reg
Write
Reg
Read Data Reg.
72
36
36
Address
Register
19 A(18:0)
Control
Logic
RPS
C
C
Reg.
Reg.
Reg. 36
36
36
CQ
CQ
Q[35:0]
Document Number: 001-57825 Rev. *N
Page 3 of 33






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