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CY7C1525KV18 CY7C1512KV18 CY7C1514KV18
72-Mbit QDR® II SRAM Two-Word Burst Architecture
72-Mbit QDR® II SRAM Two-Word Burst Architecture
Features
■ Separate independent read and write data ports ❐ Supports concurrent transactions
■ 350 MHz clock for high bandwidth
■ Two-word burst on all accesses
■ Double data rate (DDR) interfaces on both read and write ports (data transferred at 700 MHz) at 350 MHz
■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high speed systems
■ Single multiplexed address input bus latches address inputs for both read and write ports
■ Separate port selects for depth expansion ■ Synchronous internally self-timed writes ■ QDR® II operates with 1.5 cycle read latency when DOFF is
asserted HIGH ■ Operates similar to QDR I device with 1 cycle read latency whe.