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Burst Architecture. CY7C1613KV18 Datasheet

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Burst Architecture. CY7C1613KV18 Datasheet







CY7C1613KV18 Architecture. Datasheet pdf. Equivalent




CY7C1613KV18 Architecture. Datasheet pdf. Equivalent





Part

CY7C1613KV18

Description

144-Mbit QDR II SRAM Four-Word Burst Architecture

Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1613KV18 Datasheet


Cypress Semiconductor CY7C1613KV18

CY7C1613KV18; CY7C1613KV18/CY7C1615KV18 144-Mbit QDR® II SRAM Four-Word Burst Architecture 144-Mbit QDR® II SRAM Four-Word Burst Architecture Features ■ Separate inde pendent read and write data ports ❐ S upports concurrent transactions ■ 333 MHz clock for high bandwidth ■ Four- word burst for reducing address bus fre quency ■ Double Data Rate (DDR) inter faces on both read and write p.


Cypress Semiconductor CY7C1613KV18

orts (data transferred at 666 MHz) at 33 3 MHz ■ Two input clocks (K and K) fo r precise DDR timing ❐ SRAM uses risi ng edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Ec ho clocks (CQ and CQ) simplify data cap ture in high speed systems ■ Single m ultiplexed address input bus latches ad dress inputs for read and wr.


Cypress Semiconductor CY7C1613KV18

ite ports ■ Separate port selects for depth expansion ■ Synchronous interna lly self-timed writes ■ Quad data rat e (QDR®) II operates with 1.5-cycle re ad latency when DOFF is asserted high Operates similar to a QDR I device w ith .



Part

CY7C1613KV18

Description

144-Mbit QDR II SRAM Four-Word Burst Architecture

Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1613KV18 Datasheet




 CY7C1613KV18
CY7C1613KV18/CY7C1615KV18
144-Mbit QDR® II SRAM Four-Word
Burst Architecture
144-Mbit QDR® II SRAM Four-Word Burst Architecture
Features
Separate independent read and write data ports
Supports concurrent transactions
333 MHz clock for high bandwidth
Four-word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Single multiplexed address input bus latches address inputs
for read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
Quad data rate (QDR®) II operates with 1.5-cycle read latency
when DOFF is asserted high
Operates similar to a QDR I device with one-cycle read latency
when DOFF is asserted low
Available in × 18, and × 36 configurations
Full data coherency, providing most current data
Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD
Supports both 1.5 V and 1.8 V I/O supply
Available in 165-ball fine-pitch ball grid array (FBGA) package
(15 × 17 × 1.4 mm)
Offered in both Pb-free and non Pb-free packages
Variable drive high-speed transceiver logic (HSTL) output
buffers
JTAG 1149.1 compatible test access port (TAP)
Phase Locked Loop (PLL) for accurate data placement
Configuration
CY7C1613KV18 – 8 M × 18
CY7C1615KV18 – 4 M × 36
Functional Description
The CY7C1613KV18, and CY7C1615KV18 are 1.8-V
synchronous pipelined SRAMs, equipped with QDR® II
architecture. QDR II architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II architecture has separate data inputs and
data outputs to completely eliminate the need to “turn around”
the data bus that exists with common I/O devices. Each port can
be accessed through a common address bus. Addresses for
read and write addresses are latched on alternate rising edges
of the input (K) clock. Accesses to the QDR II read and write
ports are completely independent of one another. To maximize
data throughput, both read and write ports are equipped with
DDR interfaces. Each address location is associated with four
18-bit words (CY7C1613KV18), or 36-bit words
(CY7C1615KV18) that burst sequentially into or out of the
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K and C
and C), memory bandwidth is maximized while simplifying
system design by eliminating bus “turnarounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum operating frequency
Maximum operating current
Description
× 18
× 36
333 MHz
333
760
1010
300 MHz
300
710
950
250 MHz Unit
250 MHz
Not Offered mA
830
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-44273 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 30, 2015





 CY7C1613KV18
CY7C1613KV18/CY7C1615KV18
Logic Block Diagram – CY7C1613KV18
D[17:0]
18
A(20:0) 21
Address
Register
Write Write Write Write
Reg Reg Reg Reg
Address
Register
21 A(20:0)
K
K
DOFF
VREF
WPS
BWS[1:0]
CLK
Gen.
Control
Logic
Read Data Reg.
72
36
36
Control
Logic
RPS
C
C
Reg.
Reg.
Reg. 18
18
18
18
18
CQ
CQ
Q[17:0]
Logic Block Diagram – CY7C1615KV18
D[35:0]
36
A(19:0) 20
Address
Register
K
K
DOFF
VREF
WPS
BWS[3:0]
CLK
Gen.
Control
Logic
Write Write Write Write
Reg Reg Reg Reg
Address
Register
20 A(19:0)
Read Data Reg.
144
72
72
Control
Logic
RPS
C
C
Reg.
Reg.
Reg. 36
36
36
36
36
CQ
CQ
Q[35:0]
Document Number: 001-44273 Rev. *K
Page 2 of 32





 CY7C1613KV18
CY7C1613KV18/CY7C1615KV18
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Read Operations ......................................................... 6
Write Operations ......................................................... 6
Byte Write Operations ................................................. 7
Single Clock Mode ...................................................... 7
Concurrent Transactions ............................................. 7
Depth Expansion ......................................................... 7
Programmable Impedance .......................................... 7
Echo Clocks ................................................................ 7
PLL .............................................................................. 7
Application Example ........................................................ 8
Truth Table ........................................................................ 9
Write Cycle Descriptions ............................................... 10
Write Cycle Descriptions ............................................... 11
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 12
Disabling the JTAG Feature ...................................... 12
Test Access Port ....................................................... 12
Performing a TAP Reset ........................................... 12
TAP Registers ........................................................... 12
TAP Instruction Set ................................................... 12
TAP Controller State Diagram ....................................... 14
TAP Controller Block Diagram ...................................... 15
TAP Electrical Characteristics ...................................... 15
TAP AC Switching Characteristics ............................... 16
TAP Timing and Test Conditions .................................. 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Instruction Codes ........................................................... 18
Boundary Scan Order .................................................... 19
Power Up Sequence in QDR II SRAM ........................... 20
Power Up Sequence ................................................. 20
PLL Constraints ......................................................... 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Neutron Soft Error Immunity ......................................... 21
Electrical Characteristics ............................................... 21
DC Electrical Characteristics ..................................... 21
AC Electrical Characteristics ..................................... 23
Capacitance .................................................................... 23
Thermal Resistance ........................................................ 23
AC Test Loads and Waveforms ..................................... 23
Switching Characteristics .............................................. 24
Switching Waveforms .................................................... 26
Ordering Information ...................................................... 27
Ordering Code Definitions ......................................... 27
Package Diagram ............................................................ 28
Acronyms ........................................................................ 29
Document Conventions ................................................. 29
Units of Measure ....................................................... 29
Document History Page ................................................. 30
Sales, Solutions, and Legal Information ...................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC® Solutions ...................................................... 32
Cypress Developer Community ................................. 32
Technical Support ..................................................... 32
Document Number: 001-44273 Rev. *K
Page 3 of 32



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