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Burst Architecture. CY7C1645KV18 Datasheet

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Burst Architecture. CY7C1645KV18 Datasheet






CY7C1645KV18 Architecture. Datasheet pdf. Equivalent




CY7C1645KV18 Architecture. Datasheet pdf. Equivalent





Part

CY7C1645KV18

Description

144-Mbit QDR II+ SRAM Four-Word Burst Architecture



Feature


CY7C1643KV18/CY7C1645KV18 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) 144-Mbit QDR II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features ■ Separate independent read and write dat a ports ❐ Supports concurrent transac tions ■ 450-MHz clock for high bandwi dth ■ Four-word burst for reducing ad dress bus frequency ■ Double.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1645KV18 Datasheet


Cypress Semiconductor CY7C1645KV18

CY7C1645KV18; data rate (DDR) interfaces on both read and write ports (data transferred at 9 00 MHz) at 450 MHz ■ Available in 2.0 -clock cycle latency ■ Two input cloc ks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Echo c locks (CQ and CQ) simplify data capture in high-speed systems ■ Data valid p in (QVLD) to indicate valid data on the output ■ Single multiplexed.


Cypress Semiconductor CY7C1645KV18

address input bus latches address input s for read and write ports ■ Separate port selects for depth expansion ■ S ynchronous internally self-timed writes ■ Quad data rate (QDR®) II+ operate s with 2.0-cycle read latency when DOFF .


Cypress Semiconductor CY7C1645KV18

.

Part

CY7C1645KV18

Description

144-Mbit QDR II+ SRAM Four-Word Burst Architecture



Feature


CY7C1643KV18/CY7C1645KV18 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) 144-Mbit QDR II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features ■ Separate independent read and write dat a ports ❐ Supports concurrent transac tions ■ 450-MHz clock for high bandwi dth ■ Four-word burst for reducing ad dress bus frequency ■ Double.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1645KV18 Datasheet




 CY7C1645KV18
CY7C1643KV18/CY7C1645KV18
144-Mbit QDR® II+ SRAM Four-Word
Burst Architecture (2.0 Cycle Read Latency)
144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)
Features
Separate independent read and write data ports
Supports concurrent transactions
450-MHz clock for high bandwidth
Four-word burst for reducing address bus frequency
Double data rate (DDR) interfaces on both read and write ports
(data transferred at 900 MHz) at 450 MHz
Available in 2.0-clock cycle latency
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Data valid pin (QVLD) to indicate valid data on the output
Single multiplexed address input bus latches address inputs
for read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
Quad data rate (QDR®) II+ operates with 2.0-cycle read latency
when DOFF is asserted high
Operates similar to QDR I device with one cycle read latency
when DOFF is asserted low
Available in × 18, and × 36 configurations
Full data coherency, providing most current data
Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD [1]
Supports both 1.5-V and 1.8-V I/O supply
High-speed transceiver logic (HSTL) Inputs and variable drive
HSTL output buffers
Available in 165-ball fine pitch ball grid array (FBGA) package
(15 × 17 × 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Phase locked loop (PLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C1643KV18 – 8M × 18
CY7C1645KV18 – 4M × 36
Functional Description
The CY7C1643KV18, and CY7C1645KV18 are 1.8-V
synchronous pipelined SRAMs, equipped with QDR II+
architecture. Similar to QDR II architecture, QDR II+ architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has dedicated data
outputs to support read operations and the write port has
dedicated data inputs to support write operations. QDR II+
architecture has separate data inputs and data outputs to
completely eliminate the need to “turnaround” the data bus that
exists with common I/O devices. Each port is accessed through
a common address bus. Addresses for read and write addresses
are latched on alternate rising edges of the input (K) clock.
Accesses to the QDR II+ read and write ports are completely
independent of one another. To maximize data throughput, both
read and write ports are equipped with DDR interfaces. Each
address location is associated with four 18-bit words
(CY7C1643KV18), or 36-bit words (CY7C1645KV18) that burst
sequentially into or out of the device. Because data is transferred
into and out of the device on every rising edge of both input
clocks (K and K), memory bandwidth is maximized while
simplifying system design by eliminating bus “turnarounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum operating frequency
Maximum operating current
Description
× 18
× 36
450 MHz
450
940
1290
400 MHz
400
860
1170
Unit
MHz
mA
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4 V to VDD.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-44059 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 15, 2016




 CY7C1645KV18
CY7C1643KV18/CY7C1645KV18
Logic Block Diagram – CY7C1643KV18
D[17:0]
18
A(20:0) 21
Address
Register
Write Write Write Write
Reg Reg Reg Reg
Address
Register
21 A(20:0)
K
K
DOFF
VREF
WPS
BWS[1:0]
CLK
Gen.
Control
Logic
Read Data Reg.
72
36
36
Control
Logic
RPS
Reg.
Reg.
Reg. 18
18
18
18
18
CQ
CQ
Q[17:0]
QVLD
Logic Block Diagram – CY7C1645KV18
D[35:0]
36
A(19:0) 20
Address
Register
Write Write Write Write
Reg Reg Reg Reg
Address
Register
20 A(19:0)
K
K
DOFF
VREF
WPS
BWS[3:0]
CLK
Gen.
Control
Logic
Read Data Reg.
144
72
72
Control
Logic
RPS
Reg.
Reg.
Reg. 36
36
36
36
36
CQ
CQ
Q[35:0]
QVLD
Document Number: 001-44059 Rev. *M
Page 2 of 31




 CY7C1645KV18
CY7C1643KV18/CY7C1645KV18
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Read Operations ......................................................... 6
Write Operations ......................................................... 6
Byte Write Operations ................................................. 6
Concurrent Transactions ............................................. 7
Depth Expansion ......................................................... 7
Programmable Impedance .......................................... 7
Echo Clocks ................................................................ 7
Valid Data Indicator (QVLD) ........................................ 7
PLL .............................................................................. 7
Application Example ........................................................ 8
Truth Table ........................................................................ 9
Write Cycle Descriptions ............................................... 10
Write Cycle Descriptions ............................................... 11
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 12
Disabling the JTAG Feature ...................................... 12
Test Access Port ....................................................... 12
Performing a TAP Reset ........................................... 12
TAP Registers ........................................................... 12
TAP Instruction Set ................................................... 12
TAP Controller State Diagram ....................................... 14
TAP Controller Block Diagram ...................................... 15
TAP Electrical Characteristics ...................................... 15
TAP AC Switching Characteristics ............................... 16
TAP Timing and Test Conditions .................................. 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Instruction Codes ........................................................... 18
Boundary Scan Order .................................................... 19
Power Up Sequence in QDR II+ SRAM ......................... 20
Power Up Sequence ................................................. 20
PLL Constraints ......................................................... 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Neutron Soft Error Immunity ......................................... 21
Electrical Characteristics ............................................... 21
DC Electrical Characteristics ..................................... 21
AC Electrical Characteristics ..................................... 23
Capacitance .................................................................... 23
Thermal Resistance ........................................................ 23
AC Test Loads and Waveforms ..................................... 23
Switching Characteristics .............................................. 24
Switching Waveforms .................................................... 25
Read/Write/Deselect Sequence ................................ 25
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagram ............................................................ 27
Acronyms ........................................................................ 28
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 31
Worldwide Sales and Design Support ....................... 31
Products .................................................................... 31
PSoC®Solutions ....................................................... 31
Cypress Developer Community ................................. 31
Technical Support ..................................................... 31
Document Number: 001-44059 Rev. *M
Page 3 of 31






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