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Burst Architecture. CY7C2245KV18 Datasheet

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Burst Architecture. CY7C2245KV18 Datasheet






CY7C2245KV18 Architecture. Datasheet pdf. Equivalent




CY7C2245KV18 Architecture. Datasheet pdf. Equivalent





Part

CY7C2245KV18

Description

36-Mbit QDR II+ SRAM Four-Word Burst Architecture

Manufacture

Cypress Semiconductor

Datasheet
Download CY7C2245KV18 Datasheet


Cypress Semiconductor CY7C2245KV18

CY7C2245KV18; CY7C2245KV18 36-Mbit QDR® II+ SRAM Four -Word Burst Architecture (2.0 Cycle Rea d Latency) with ODT 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Separate independent read and write data ports ❐ Supports concurrent tran sactions ■ 450 MHz clock for high ban dwidth ■ Four-word burst for reducing address bus frequency ■ Dou.


Cypress Semiconductor CY7C2245KV18

ble data rate (DDR) interfaces on both r ead and write ports (data transferred a t 900 MHz) at 450 MHz ■ Available in 2.0 clock cycle latency ■ Two input c locks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Ech o clocks (CQ and CQ) simplify data capt ure in high speed systems ■ Data vali d pin (QVLD) to indicate valid data on the output ■ On-die terminat.


Cypress Semiconductor CY7C2245KV18

ion (ODT) feature ❐ Supported for D[x: 0], BWS[x:0], and K/K inputs ■ Single multiplexed address input bus latches address inputs for read and write ports ■ Separate port selects for depth ex pansion ■ Synchronous internally self - .



Part

CY7C2245KV18

Description

36-Mbit QDR II+ SRAM Four-Word Burst Architecture

Manufacture

Cypress Semiconductor

Datasheet
Download CY7C2245KV18 Datasheet




 CY7C2245KV18
CY7C2245KV18
36-Mbit QDR® II+ SRAM Four-Word
Burst Architecture (2.0 Cycle Read Latency) with ODT
36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Features
Separate independent read and write data ports
Supports concurrent transactions
450 MHz clock for high bandwidth
Four-word burst for reducing address bus frequency
Double data rate (DDR) interfaces on both read and write ports
(data transferred at 900 MHz) at 450 MHz
Available in 2.0 clock cycle latency
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Data valid pin (QVLD) to indicate valid data on the output
On-die termination (ODT) feature
Supported for D[x:0], BWS[x:0], and K/K inputs
Single multiplexed address input bus latches address inputs
for read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
QDR® II+ operates with 2.0 cycle read latency when DOFF is
asserted HIGH
Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted LOW
Available in × 36 configurations
Full data coherency, providing most current data
Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD [1]
Supports both 1.5 V and 1.8 V I/O supply
HSTL inputs and variable drive HSTL output buffers
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
Offered in Pb-free packages
JTAG 1149.1 compatible test access port
Phase-locked loop (PLL) for accurate data placement
Selection Guide
Maximum operating frequency
Maximum operating current
Description
Configurations
With Read Cycle Latency of 2.0 Cycles:
CY7C2245KV18 – 1M × 36
Functional Description
The CY7C2245KV18 is 1.8 V synchronous pipelined SRAM,
equipped with QDR II+ architecture. Similar to QDR II
architecture, QDR II+ architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II+ architecture has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus that exists with common I/O devices. Each port is
accessed through a common address bus. Addresses for read
and write addresses are latched on alternate rising edges of the
input (K) clock. Accesses to the QDR II+ read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 36-bit
words (CY7C2245KV18) that burst sequentially into or out of the
device. Because data is transferred into and out of the device on
every rising edge of both input clocks (K and K), memory
bandwidth is maximized while simplifying system design by
eliminating bus “turn-arounds”.
These devices have an on-die termination feature supported for
D[x:0], BWS[x:0], and K/K inputs, which helps eliminate external
termination resistors, reduce cost, reduce board area, and
simplify board routing.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
450 MHz Unit
450 MHz
× 36 1020 mA
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4 V to VDD.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-87885 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 26, 2016





 CY7C2245KV18
CY7C2245KV18
Logic Block Diagram – CY7C2245KV18
D[35:0]
36
A(17:0) 18
Address
Register
Write Write Write Write
Reg Reg Reg Reg
Address
Register
18 A(17:0)
K
K
DOFF
VREF
WPS
BWS[3:0]
CLK
Gen.
Control
Logic
Read Data Reg.
144
72
72
Control
Logic
RPS
Reg.
Reg.
Reg. 36
36
36
36
36
CQ
CQ
Q[35:0]
QVLD
Document Number: 001-87885 Rev. *C
Page 2 of 28





 CY7C2245KV18
CY7C2245KV18
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Read Operations ......................................................... 6
Write Operations ......................................................... 7
Byte Write Operations ................................................. 7
Concurrent Transactions ............................................. 7
Depth Expansion ......................................................... 7
Programmable Impedance .......................................... 7
Echo Clocks ................................................................ 7
Valid Data Indicator (QVLD) ........................................ 7
On-Die Termination (ODT) .......................................... 7
PLL .............................................................................. 7
Application Example ........................................................ 8
Truth Table ........................................................................ 9
Write Cycle Descriptions ............................................... 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port ....................................................... 11
Performing a TAP Reset ........................................... 11
TAP Registers ........................................................... 11
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Electrical Characteristics ...................................... 14
TAP AC Switching Characteristics ............................... 15
TAP Timing and Test Conditions .................................. 16
Identification Register Definitions ................................ 17
Scan Register Sizes ....................................................... 17
Instruction Codes ........................................................... 17
Boundary Scan Order .................................................... 18
Power Up Sequence in QDR II+ SRAM ......................... 19
Power Up Sequence ................................................. 19
PLL Constraints ......................................................... 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
Neutron Soft Error Immunity ......................................... 20
Electrical Characteristics ............................................... 20
DC Electrical Characteristics ..................................... 20
AC Electrical Characteristics ..................................... 21
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
AC Test Loads and Waveforms ..................................... 21
Switching Characteristics .............................................. 22
Switching Waveforms .................................................... 23
Read/Write/Deselect Sequence ................................ 23
Ordering Information ...................................................... 24
Ordering Code Definitions ......................................... 24
Package Diagram ............................................................ 25
Acronyms ........................................................................ 26
Document Conventions ................................................. 26
Units of Measure ....................................................... 26
Document History Page ................................................. 27
Sales, Solutions, and Legal Information ...................... 28
Worldwide Sales and Design Support ....................... 28
Products .................................................................... 28
PSoC®Solutions ....................................................... 28
Cypress Developer Community ................................. 28
Technical Support ..................................................... 28
Document Number: 001-87885 Rev. *C
Page 3 of 28



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