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Burst Architecture. CY7C25422KV18 Datasheet

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Burst Architecture. CY7C25422KV18 Datasheet






CY7C25422KV18 Architecture. Datasheet pdf. Equivalent




CY7C25422KV18 Architecture. Datasheet pdf. Equivalent





Part

CY7C25422KV18

Description

72-Mbit QDR II+ SRAM Two-Word Burst Architecture



Feature


CY7C25422KV18 72-Mbit QDR® II+ SRAM Two -Word Burst Architecture (2.0 Cycle Rea d Latency) with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 C ycle Read Latency) with ODT Features Separate independent read and write d ata ports ❐ Supports concurrent trans actions ■ 333 MHz clock for high band width ■ Two-word burst for reducing a ddress bus frequency ■ Doubl.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C25422KV18 Datasheet


Cypress Semiconductor CY7C25422KV18

CY7C25422KV18; e Data Rate (DDR) interfaces on both rea d and write ports (data transferred at 666 MHz) at 333 MHz ■ Available in 2. 0 clock cycle latency ■ Two input clo cks (K and K) for precise DDR timing SRAM uses rising edges only ■ Echo clocks (CQ and CQ) simplify data captur e in high speed systems ■ Data valid pin (QVLD) to indicate valid data on th e output ■ On-Die Terminatio.


Cypress Semiconductor CY7C25422KV18

n (ODT) feature ❐ Supported for D[x:0] , BWS[x:0], and K/K inputs ■ Single m ultiplexed address input bus latches ad dress inputs for both read and write po rts ■ Separate port selects for depth expansion ■ Synchronous internally s e .


Cypress Semiconductor CY7C25422KV18

.

Part

CY7C25422KV18

Description

72-Mbit QDR II+ SRAM Two-Word Burst Architecture



Feature


CY7C25422KV18 72-Mbit QDR® II+ SRAM Two -Word Burst Architecture (2.0 Cycle Rea d Latency) with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 C ycle Read Latency) with ODT Features Separate independent read and write d ata ports ❐ Supports concurrent trans actions ■ 333 MHz clock for high band width ■ Two-word burst for reducing a ddress bus frequency ■ Doubl.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C25422KV18 Datasheet




 CY7C25422KV18
CY7C25422KV18
72-Mbit QDR® II+ SRAM Two-Word
Burst Architecture (2.0 Cycle Read Latency) with ODT
72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
Features
Separate independent read and write data ports
Supports concurrent transactions
333 MHz clock for high bandwidth
Two-word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz
Available in 2.0 clock cycle latency
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Data valid pin (QVLD) to indicate valid data on the output
On-Die Termination (ODT) feature
Supported for D[x:0], BWS[x:0], and K/K inputs
Single multiplexed address input bus latches address inputs
for both read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
QDR® II+ operates with 2.0 cycle read latency when DOFF is
asserted HIGH
Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted LOW
Available in × 18 configurations
Full data coherency, providing most current data
Core VDD = 1.8 V± 0.1 V; VDDQ = 1.4 V to VDD [1]
Supports both 1.5 V and 1.8 V supply
HSTL inputs and variable drive HSTL output buffers
Available in 165-Ball FBGA package (13 × 15 × 1.4 mm)
Offered in Pb-free packages
JTAG 1149.1 compatible test access port
Phase Locked Loop (PLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C25422KV18 – 4M × 18
Functional Description
The CY7C25422KV18 are 1.8 V Synchronous Pipelined
SRAMs, equipped with QDR® II+ architecture. Similar to QDR II
architecture, QDR II+ architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II+ architecture has separate data inputs and
data outputs to completely eliminate the need to “turnaround” the
data bus that exists with common devices. Access to each port
is through a common address bus. Addresses for read and write
addresses are latched on alternate rising edges of the input (K)
clock. Accesses to the QDR II+ read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with two 18-bit
words (CY7C25422KV18) that burst sequentially into or out of
the device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K),
memory bandwidth is maximized while simplifying system
design by eliminating bus “turnarounds”.
These devices have an On-Die Termination feature supported
for D[x:0], BWS[x:0], and K/K inputs, which helps eliminate
external termination resistors, reduce cost, reduce board area,
and simplify board routing.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
Description
333 MHz Unit
333 MHz
× 18 810 mA
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4V to VDD.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-90368 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 3, 2018




 CY7C25422KV18
CY7C25422KV18
Logic Block Diagram – CY7C25422KV18
D[17:0]
18
A(20:0) 21
Address
Register
K
K
DOFF
VREF
WPS
BWS[1:0]
CLK
Gen.
Control
Logic
Write
Reg
Write
Reg
Address
Register
21 A(20:0)
Read Data Reg.
36
18
18
Control
Logic
RPS
Reg.
Reg.
Reg. 18
18
18
CQ
CQ
Q[17:0]
QVLD
Document Number: 001-90368 Rev. *D
Page 2 of 28




 CY7C25422KV18
CY7C25422KV18
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 7
Read Operations ......................................................... 7
Write Operations ......................................................... 7
Byte Write Operations ................................................. 7
Concurrent Transactions ............................................. 7
Depth Expansion ......................................................... 7
Programmable Impedance .......................................... 7
Echo Clocks ................................................................ 7
Valid Data Indicator (QVLD) ........................................ 7
On-Die Termination (ODT) .......................................... 8
PLL .............................................................................. 8
Application Example ........................................................ 8
Truth Table ........................................................................ 9
Write Cycle Descriptions ................................................. 9
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 10
Disabling the JTAG Feature ...................................... 10
Test Access Port ....................................................... 10
Performing a TAP Reset ........................................... 10
TAP Registers ........................................................... 10
TAP Instruction Set ................................................... 10
TAP Controller State Diagram ....................................... 12
TAP Controller Block Diagram ...................................... 13
TAP Electrical Characteristics ...................................... 13
TAP AC Switching Characteristics ............................... 14
TAP Timing and Test Conditions .................................. 15
Identification Register Definitions ................................ 16
Scan Register Sizes ....................................................... 16
Instruction Codes ........................................................... 16
Boundary Scan Order .................................................... 17
Power Up Sequence in QDR II+ SRAM ......................... 18
Power Up Sequence ................................................. 18
PLL Constraints ......................................................... 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
Neutron Soft Error Immunity ......................................... 19
Electrical Characteristics ............................................... 19
DC Electrical Characteristics ..................................... 19
AC Electrical Characteristics ..................................... 20
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
AC Test Loads and Waveforms ..................................... 21
Switching Characteristics .............................................. 22
Switching Waveforms .................................................... 23
Read/Write/Deselect Sequence ................................ 23
Ordering Information ...................................................... 24
Ordering Code Definitions ......................................... 24
Package Diagram ............................................................ 25
Acronyms ........................................................................ 26
Document Conventions ................................................. 26
Units of Measure ....................................................... 26
Document History Page ................................................. 27
Sales, Solutions, and Legal Information ...................... 28
Worldwide Sales and Design Support ....................... 28
Products .................................................................... 28
PSoC® Solutions ...................................................... 28
Cypress Developer Community ................................. 28
Technical Support ..................................................... 28
Document Number: 001-90368 Rev. *D
Page 3 of 28






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