72-Mbit QDR II+ SRAM Two-Word Burst Architecture
CY7C25422KV18
72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
72-Mbit QDR® II+ SRAM...
Description
CY7C25422KV18
72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
Features
■ Separate independent read and write data ports ❐ Supports concurrent transactions
■ 333 MHz clock for high bandwidth
■ Two-word burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
■ Available in 2.0 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ On-Die Termination (ODT) feature ❐ Supported for D[x:0], BWS[x:0], and K/K inputs
■ Single multiplexed address input bus latches address inputs for both read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally se...
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