Document
CY7C25632KV18 CY7C25652KV18
72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Features
■ Separate independent read and write data ports ❐ Supports concurrent transactions
■ 550 MHz clock for high bandwidth
■ Four-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces on both read and write ports
(data transferred at 1100 MHz) at 550 MHz
■ Available in 2.5 clock cycle latency ■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only ■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output ■ On-die termination (ODT) feature
❐ Supported for D[x:0], BWS[x:0], and K/K inputs ■ Single multiplexed address input bus latches address inputs
for read and write ports
■ Separate port selects for depth expansion ■ Synchronous .