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Burst Architecture. CYRS1545AV18 Datasheet

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Burst Architecture. CYRS1545AV18 Datasheet







CYRS1545AV18 Architecture. Datasheet pdf. Equivalent




CYRS1545AV18 Architecture. Datasheet pdf. Equivalent





Part

CYRS1545AV18

Description

72-Mbit QDR II+ SRAM Four-Word Burst Architecture

Manufacture

Cypress Semiconductor

Datasheet
Download CYRS1545AV18 Datasheet


Cypress Semiconductor CYRS1545AV18

CYRS1545AV18; 72-Mbit QDR® II+ SRAM Four-Word Burst A rchitecture with RadStop™ Technology Radiation Performance Radiation Data Total Dose =300 Krad ■ Soft erro r rate (both Heavy Ion and proton) Heav y ions  1 × 10-10 upsets/bit-day wi th an external SECDED EDAC Controller Neutrons = 2.0 × 1014 N/cm2 ■ Dos e rate = 2.0 × 109 rad(Si)/sec ■ Dos e rate survivability (rad(Si)/sec) = 1.


Cypress Semiconductor CYRS1545AV18

.5 × 10^11 (rad(Si)/sec ■ Latch up im munity = 120 MeV.cm2/mg (125 °C) Proto typing Options ■ Non-qualified CYPT15 43AV18, and CYPT1545AV18 devices with s ame functional and timing characteristi cs in a 165-ball Ceramic Column Grid Ar ray (CCGA) package and Land Grid Array (LGA) package without solder columns at tached. Features ■ Separate independe nt read and write data por.


Cypress Semiconductor CYRS1545AV18

ts ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth Four-word burst for reducing address bus frequency ■ Double data rate (DDR ) interfaces on both read and write por ts at 250 MHz (data transferred at 500 MHz) ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses risin g edges only ■ Echo clocks (CQ and CQ ) simplify data capture in high .



Part

CYRS1545AV18

Description

72-Mbit QDR II+ SRAM Four-Word Burst Architecture

Manufacture

Cypress Semiconductor

Datasheet
Download CYRS1545AV18 Datasheet




 CYRS1545AV18
72-Mbit QDR® II+ SRAM Four-Word Burst Architecture with RadStop™ Technology
Radiation Performance
Radiation Data
Total Dose =300 Krad
Soft error rate (both Heavy Ion and proton)
Heavy ions 1 × 10-10 upsets/bit-day with an external SECDED
EDAC Controller
Neutrons = 2.0 × 1014 N/cm2
Dose rate = 2.0 × 109 rad(Si)/sec
Dose rate survivability (rad(Si)/sec) = 1.5 × 10^11 (rad(Si)/sec
Latch up immunity = 120 MeV.cm2/mg (125 °C)
Prototyping Options
Non-qualified CYPT1543AV18, and CYPT1545AV18 devices
with same functional and timing characteristics in a
165-ball Ceramic Column Grid Array (CCGA) package and
Land Grid Array (LGA) package without solder columns
attached.
Features
Separate independent read and write data ports
Supports concurrent transactions
250 MHz clock for high bandwidth
Four-word burst for reducing address bus frequency
Double data rate (DDR) interfaces on both read and write ports
at 250 MHz (data transferred at 500 MHz)
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Single multiplexed address input bus latches address inputs
for read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
QDR® II+ operates with 2.0 cycle read latency when the delay
lock loop (DLL) is enabled
Available in × 18, and × 36 configurations
Full data coherency, providing most current data
Core VDD = 1.8 (± 0.1 V); I/O VDDQ = 1.4 V to VDD
Available in 165-ball CCGA (21 × 25 × 2.83 mm)
CYRS1543AV18
CYRS1545AV18
72-Mbit QDR® II+ SRAM
Four-Word Burst Architecture
with RadStop™ Technology
HSTL inputs and variable drive HSTL output buffers
JTAG 1149.1 compatible test access port
DLL for accurate data placement
Configurations
CYRS1543AV18 – 4M × 18
CYRS1545AV18 – 2M × 36
Functional Description
The CYRS1543AV18 and CYRS1545AV18 are synchronous
pipelined SRAMs, equipped with 1.8 V QDR II+ architecture with
RadStop™ technology. Cypress’s state-of-the-art RadStop
Technology is radiation hardened through proprietary design and
process hardening techniques.
The QDR II+ architecture consists of two separate ports: the read
port and the write port to access the memory array. The read port
has dedicated data outputs to support read operations and the
write port has dedicated data inputs to support write operations.
QDR II+ architecture has separate data inputs and data outputs
to completely eliminate the need to turnaround the data bus that
exists with common I/O devices. Each port can be accessed
through a common address bus. Addresses for read and write
addresses are latched on alternate rising edges of the input (K)
clock. Accesses to the QDR II+ read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 18-bit
words (CYRS1543AV18) or 36-bit words (CYRS1545AV18) that
burst sequentially into or out of the device. Because data can be
transferred into and out of the device on every rising edge of both
input clocks (K and K), memory bandwidth is maximized while
simplifying system design by eliminating bus turnarounds.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
For a complete list of related resources, click here.
Selection Guide
Description
Maximum operating frequency
Maximum operating current (125 °C,
concurrent R/W)
× 18
× 36
250 MHz
250
1275
1275
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-60007 Rev. *N
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 27, 2019





 CYRS1545AV18
CYRS1543AV18
CYRS1545AV18
Logic Block Diagram – CYRS1543AV18
D[17:0]
18
A(19:0) 20
Address
Register
Write Write Write Write
Reg Reg Reg Reg
Address
Register
20 A(19:0)
K
K
DOFF
VREF
WPS
BWS[1:0]
CLK
Gen.
Control
Logic
Read Data Reg.
72
36
36
Control
Logic
RPS
Reg.
Reg.
Reg. 18
18
18
18
18
CQ
CQ
Q[17:0]
QVLD
Logic Block Diagram – CYRS1545AV18
D[35:0]
36
A(18:0) 19
Address
Register
Write Write Write Write
Reg Reg Reg Reg
Address
Register
19 A(18:0)
K
K
DOFF
VREF
WPS
BWS[3:0]
CLK
Gen.
Control
Logic
Read Data Reg.
144
72
72
Control
Logic
RPS
Reg.
Reg.
Reg. 36
36
36
36
36
CQ
CQ
Q[35:0]
QVLD
Document Number: 001-60007 Rev. *N
Page 2 of 35





 CYRS1545AV18
CYRS1543AV18
CYRS1545AV18
Contents
Manufacturing Flow .......................................................... 4
Radiation Hardened Design ........................................ 4
Neutron Soft Error Immunity ........................................... 4
Pin Configuration ............................................................. 5
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 8
Read Operations ......................................................... 8
Write Operations ......................................................... 8
Byte Write Operations ................................................. 8
Concurrent Transactions ............................................. 8
Depth Expansion ......................................................... 9
Programmable Impedance .......................................... 9
Echo Clocks ................................................................ 9
Valid Data Indicator (QVLD) ........................................ 9
DLL .............................................................................. 9
Qualification and Screening ........................................ 9
Application Example ...................................................... 10
Truth Table ...................................................................... 11
Write Cycle Descriptions ............................................... 11
Write Cycle Descriptions ............................................... 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port ....................................................... 13
Performing a TAP Reset ........................................... 13
TAP Registers ........................................................... 13
TAP Instruction Set ................................................... 13
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 16
TAP Electrical Characteristics ...................................... 16
TAP AC Switching Characteristics ............................... 17
TAP Timing and Test Conditions .................................. 18
Identification Register Definitions ................................ 19
Scan Register Sizes ....................................................... 19
Instruction Codes ........................................................... 19
Boundary Scan Order .................................................... 20
Power Up Sequence in QDR II+ SRAM ......................... 21
Power Up Sequence ................................................. 21
DLL Constraints ......................................................... 21
Maximum Ratings ........................................................... 22
Operating Range ............................................................. 22
Electrical Characteristics ............................................... 22
DC Electrical Characteristics ..................................... 22
AC Electrical Characteristics ..................................... 23
Radiation Performance .................................................. 23
Capacitance .................................................................... 23
Thermal Resistance ........................................................ 23
AC Test Loads and Waveforms ..................................... 24
Switching Characteristics .............................................. 25
Switching Waveforms .................................................... 26
Ordering Information ...................................................... 27
Ordering Code Definitions ......................................... 27
Package Diagrams .......................................................... 28
Acronyms ........................................................................ 30
Document Conventions ................................................. 30
Units of Measure ....................................................... 30
Glossary .......................................................................... 31
Document History Page ................................................. 32
Sales, Solutions, and Legal Information ...................... 35
Worldwide Sales and Design Support ....................... 35
Products .................................................................... 35
PSoC® Solutions ...................................................... 35
Cypress Developer Community ................................. 35
Technical Support ..................................................... 35
Document Number: 001-60007 Rev. *N
Page 3 of 35



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