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Static RAM. CYDM128B16 Datasheet

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Static RAM. CYDM128B16 Datasheet






CYDM128B16 RAM. Datasheet pdf. Equivalent




CYDM128B16 RAM. Datasheet pdf. Equivalent





Part

CYDM128B16

Description

1.8 V 4 K/8 K/16 K x 16 MoBL Dual-Port Static RAM

Manufacture

Cypress Semiconductor

Datasheet
Download CYDM128B16 Datasheet


Cypress Semiconductor CYDM128B16

CYDM128B16; CYDM064B16 CYDM128B16 CYDM256B16 1.8 V 4 K/8 K/16 K × 16 MoBL® Dual-Port Stat ic RAM 1.8V 4K/8K/16K x 16 MoBL® Dual -Port Static RAM Features ■ True dual ported memory cells that allow simulta neous access of the same memory locatio n ■ 4, 8, or 16K × 16 organization Ultra Low operating power ❐ Active : ICC = 15 mA (typical) at 55 ns ❐ St andby: ISB3 = 2 A (typical) ■ S.


Cypress Semiconductor CYDM128B16

mall footprint: available in a 6x6 mm 10 0-pin Pb-free vfBGA ■ Port independen t 1.8V, 2.5V, and 3.0V I/Os ■ Full as ynchronous operation ■ Automatic powe r down ■ Pin select for Master or Sla ve ■ Expandable data bus to 32-bits with Master or Slave chip select when u sing more than one device ■ On-chip a rbitration logic ■ Semaphores include d to permit software handshaking.


Cypress Semiconductor CYDM128B16

between ports ■ Input read registers and output drive registers ■ INT flag for port-to-port communication ■ Sep arate upper-byte and lower-byte control ■ Industrial temperature ranges Sel ection Guide for VCC = 1.8V Para .



Part

CYDM128B16

Description

1.8 V 4 K/8 K/16 K x 16 MoBL Dual-Port Static RAM

Manufacture

Cypress Semiconductor

Datasheet
Download CYDM128B16 Datasheet




 CYDM128B16
CYDM064B16
CYDM128B16
CYDM256B16
1.8 V, 4K/8K/16K × 16 MoBL® Dual-Port
Static RAM
1.8 V, 4K/8K/16K × 16 MoBL® Dual-Port Static RAM
Features
True dual ported memory cells that allow simultaneous access
of the same memory location
4, 8, or 16K × 16 organization
Ultra Low operating power
Active: ICC = 15 mA (typical) at 55 ns
Standby: ISB3 = 2 A (typical)
Small footprint: available in a 6 × 6 mm 100-pin Pb-free vfBGA
Port independent 1.8 V, 2.5 V, and 3.0 V I/Os
Full asynchronous operation
Automatic power down
Pin select for Master or Slave
Expandable data bus to 32-bits with Master or Slave chip select
when using more than one device
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
Input read registers and output drive registers
INT flag for port-to-port communication
Separate upper-byte and lower-byte control
Industrial temperature ranges
Functional Description
The CYDM256B16, CYDM128B16, and CYDM064B16 are low
power CMOS 4K, 8K,16K × 16 dual-port static RAMs. Arbitration
schemes are included on the devices to handle situations when
multiple processors access the same piece of data. Two ports
are provided that permit independent, asynchronous access for
reads and writes to any location in memory. The devices can be
used as standalone 16-bit dual-port static RAMs or multiple
devices can be combined to function as a 32-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 32-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor or multi-
processor designs, communications status buffering, and
dual-port video or graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY indicates that the
port is trying to access the same location currently being
accessed by the other port. The Interrupt flag (INT) permits
communication between ports or systems through a mail box.
The semaphores are used to pass a flag or token, from one port
to the other, to indicate that a shared resource is in use. The
semaphore logic consists of eight shared latches. Only one side
can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a Chip Enable (CE) pin.
The CYDM256B16, CYDM128B16, CYDM064B16 are available
in 100-ball 0.5 mm pitch Ball Grid Array (BGA) packages.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-00217 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 12, 2018





 CYDM128B16
CYDM064B16
CYDM128B16
CYDM256B16
Selection Guide for VCC = 1.8V
Parameter
CYDM256B16/CYDM128B16/CYDM064B16
(-55)
Port I/O Voltages (P1–P2)
1.8 V–1.8 V
Maximum Access Time
55
Typical Operating Current
15
Typical Standby Current for ISB1
Typical Standby Current for ISB3
2
2
Selection Guide for VCC = 2.5 V
Parameter
CYDM256B16/CYDM128B16/CYDM064B16
(-55)
Port I/O Voltages (P1–P2)
2.5 V–2.5 V
Maximum Access Time
55
Typical Operating Current
28
Typical Standby Current for ISB1
Typical Standby Current for ISB3
6
4
Selection Guide for VCC = 3.0 V
Parameter
CYDM256B16/CYDM128B16/CYDM064B16
(-55)
Port I/O Voltages (P1–P2)
3.0 V–3.0 V
Maximum Access Time
55
Typical Operating Current
42
Typical Standby Current for ISB1
Typical Standby Current for ISB3
7
6
Unit
V
ns
mA
A
A
Unit
V
ns
mA
A
A
Unit
V
ns
mA
A
A
Document Number: 001-00217 Rev. *K
Page 2 of 33





 CYDM128B16
Logic Block Diagram [1, 2]
IO[15:0]L
UBL
LBL
IO
Control
CYDM064B16
CYDM128B16
CYDM256B16
IO
Control
IO[15:0]R
UBR
LBR
16K X 16
Dual Ported Array
A[13:0]L
CE L
OE L
R/W L
SEML
BUSY L
INTL
IRR0 ,IRR1
Address Decode
Address Decode
Mailboxes
CEL
OEL
R/WL
Interrupt
Arbitration
Semaphore
INTR
M/S
Input Read
Register and
Output Drive
Register
SFEN
CE R
OE R
R/W R
ODR0 - ODR4
A [13:0]R
CE R
OE R
R/W R
SEMR
BUSY R
Notes
1. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices.
2. BUSY is an output in master mode and an input in slave mode.
Document Number: 001-00217 Rev. *K
Page 3 of 33



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