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Static RAM. CY62168GE Datasheet

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Static RAM. CY62168GE Datasheet






CY62168GE RAM. Datasheet pdf. Equivalent




CY62168GE RAM. Datasheet pdf. Equivalent





Part

CY62168GE

Description

16-Mbit (2M words x 8 bits) Static RAM



Feature


CY62168G/CY62168GE MoBL® 16-Mbit (2M wo rds × 8 bits) Static RAM with Error-Co rrecting Code (ECC) 16-Mbit (2M words × 8 bits) Static RAM with Error-Correc ting Code (ECC) Features ■ Ultra-low standby power ❐ Typical standby curre nt: 5.5 A ❐ Maximum standby curren t: 16 A ■ High speed: 45 ns/55 ns ■ Embedded error-correcting code (ECC ) for single-bit error correction ■.
Manufacture

Cypress Semiconductor

Datasheet
Download CY62168GE Datasheet


Cypress Semiconductor CY62168GE

CY62168GE; Wide voltage range: 1.65 V to 2.2 V, 2. 2 V to 3.6 V, 4.5 V to 5.5 V ■ 1.0 V data retention ■ Transistor-transisto r logic (TTL) compatible inputs and out puts ■ ERR pin to indicate 1-bit erro r detection and correction ■ Availabl e in Pb-free 48-ball VFBGA package Func tional Description CY62168G and CY62168 GE are high-performance CMOS low-power (MoBL) SRAM devices with e.


Cypress Semiconductor CY62168GE

mbedded ECC. Both devices are offered in single and dual chip enable options an d in multiple pin configurations. The C Y62168GE device includes an error indic ation pin that signals a single-bit err or-detection and correction event dur .


Cypress Semiconductor CY62168GE

.

Part

CY62168GE

Description

16-Mbit (2M words x 8 bits) Static RAM



Feature


CY62168G/CY62168GE MoBL® 16-Mbit (2M wo rds × 8 bits) Static RAM with Error-Co rrecting Code (ECC) 16-Mbit (2M words × 8 bits) Static RAM with Error-Correc ting Code (ECC) Features ■ Ultra-low standby power ❐ Typical standby curre nt: 5.5 A ❐ Maximum standby curren t: 16 A ■ High speed: 45 ns/55 ns ■ Embedded error-correcting code (ECC ) for single-bit error correction ■.
Manufacture

Cypress Semiconductor

Datasheet
Download CY62168GE Datasheet




 CY62168GE
CY62168G/CY62168GE MoBL®
16-Mbit (2M words × 8 bits) Static RAM
with Error-Correcting Code (ECC)
16-Mbit (2M words × 8 bits) Static RAM with Error-Correcting Code (ECC)
Features
Ultra-low standby power
Typical standby current: 5.5 A
Maximum standby current: 16 A
High speed: 45 ns/55 ns
Embedded error-correcting code (ECC) for single-bit error
correction
Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V
1.0 V data retention
Transistor-transistor logic (TTL) compatible inputs and outputs
ERR pin to indicate 1-bit error detection and correction
Available in Pb-free 48-ball VFBGA package
Functional Description
CY62168G and CY62168GE are high-performance CMOS
low-power (MoBL) SRAM devices with embedded ECC. Both
devices are offered in single and dual chip enable options and in
multiple pin configurations. The CY62168GE device includes an
error indication pin that signals a single-bit error-detection and
correction event during a read cycle.
Devices with a single chip enable input are accessed by
asserting the chip enable input (CE) LOW. Dual chip enable
devices are accessed by asserting both chip enable inputs – CE1
as LOW and CE2 as HIGH.
Write to the device by taking Chip Enable 1 (CE1) LOW and
Chip Enable 2 (CE2) HIGH and the Write Enable (WE) input
LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written
into the location specified on the address pins (A0 through A20).
Read from the device by taking Chip Enable 1 (CE1) and
Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH while
forcing Write Enable (WE) HIGH. Under these conditions, the
contents of the memory location specified by the address pins
will appear on the I/O pins.
The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a
write operation is in progress (CE1 LOW and CE2 HIGH and WE
LOW). See the Truth Table – CY62168G/CY62168GE on page
14 for a complete description of read and write modes.
On CY62168GE devices, the detection and correction of a single
bit error in the accessed location is indicated by the assertion of
the ERR output (ERR = HIGH) [1].
The CY62168G and CY62168GE devices are available in a
Pb-free 48-pin VFBGA package. The logic block diagrams are
on page 2.
For a complete list of related resources, click here.
Product Portfolio
Product
Features and Options
(see Pin
Configurations
section)
Range
CY62168G(E)18 Single or dual Chip
Enables
CY62168G(E)30
CY62168G(E) Optional ERR pin
Industrial
VCC Range (V)
1.65 V–2.2 V
2.2 V–3.6 V
4.5 V–5.5 V
Power Dissipation
Speed
(ns)
Operating ICC, (mA)
f = fmax
Typ[2]
Max
Standby, ISB2 (µA)
Typ[2]
Max
55 29
32
7
26
45 29 36 5.5 16
Notes
1. This device does not support automatic write-back on error detection.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC = 3 V
(for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-84771 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 3, 2016




 CY62168GE
Logic Block Diagram – CY62168G
ECC ENCODER
DATAIN 
DRIVERS
A0
A1
A2
A3
A4
A5
2M x 8
RAM ARRAY
A6
A7
A8
A9
COLUMN 
DECODER
CY62168G/CY62168GE MoBL®
I/O0I/O7
WE CE2
OE CE1
Logic Block Diagram – CY62168GE
ECC ENCODER
DATAIN 
DRIVERS
A0
A1
A2
A3
A4
A5
2M x 8
RAM ARRAY
A6
A7
A8
A9
COLUMN 
DECODER
I/O0I/O7
ERR
WE CE2
OE CE1
Document Number: 001-84771 Rev. *H
Page 2 of 19




 CY62168GE
CY62168G/CY62168GE MoBL®
Contents
Pin Configurations ........................................................... 4
Maximum Ratings ............................................................. 5
Operating Range ............................................................... 5
DC Electrical Characteristics .......................................... 5
Capacitance ...................................................................... 7
Thermal Resistance .......................................................... 7
AC Test Loads and Waveforms ....................................... 7
Data Retention Characteristics ....................................... 8
Data Retention Waveform ................................................ 8
Switching Characteristics ................................................ 9
Switching Waveforms .................................................... 10
Truth Table – CY62168G/CY62168GE ........................... 14
ERR Output – CY62168GE ............................................. 14
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagrams .......................................................... 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC®Solutions ....................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Document Number: 001-84771 Rev. *H
Page 3 of 19






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