DatasheetsPDF.com

Static RAM. CY7S1061G Datasheet

DatasheetsPDF.com

Static RAM. CY7S1061G Datasheet







CY7S1061G RAM. Datasheet pdf. Equivalent




CY7S1061G RAM. Datasheet pdf. Equivalent





Part

CY7S1061G

Description

16-Mbit (1 M words x 16 bit) Static RAM

Manufacture

Cypress Semiconductor

Datasheet
Download CY7S1061G Datasheet


Cypress Semiconductor CY7S1061G

CY7S1061G; CY7S1061G/CY7S1061GE 16-Mbit (1 M words × 16 bit) Static RAM with PowerSnooze and ECC 16-Mbit (1 M words × 16 bi t) Static RAM with PowerSnooze™ and E rror Correcting Code (ECC) Features ■ High speed ❐ tAA = 10 ns ■ Ultra-l ow power PowerSnooze™[1] device ❐ D eep Sleep (DS) current IDS = 22-µA max imum ■ Low active and standby current s ❐ ICC = 90-mA typical ❐ ISB2 = 20-m.


Cypress Semiconductor CY7S1061G

A typical ■ Wide operating voltage ran ge: 1.65 V to 2.2 V, 2.2 V to 3.6 V, an d 4.5 V to 5.5 V ■ Embedded error-cor recting code (ECC) for single-bit error correction ■ 1.0-V data retention Transistor-transistor logic (TTL) com patible inputs and outputs ■ Error in dication (ERR) pin to indicate 1-bit er ror detection and correction ■ Availa ble in Pb-free 48-pin TSOP I, .


Cypress Semiconductor CY7S1061G

54-pin TSOP II, and 48-ball VFBGA packag es Functional Description The CY7S1061G /CY7S1061GE is a high-performance CMOS fast static RAM organized as 1,048,576 words by 16 bits. This device features fast access times (10 ns) and .



Part

CY7S1061G

Description

16-Mbit (1 M words x 16 bit) Static RAM

Manufacture

Cypress Semiconductor

Datasheet
Download CY7S1061G Datasheet




 CY7S1061G
CY7S1061G/CY7S1061GE
16-Mbit (1 M words × 16 bit) Static RAM
with PowerSnooze™ and ECC
16-Mbit (1 M words × 16 bit) Static RAM with PowerSnooze™ and Error Correcting Code (ECC)
Features
High speed
tAA = 10 ns
Ultra-low power PowerSnooze™[1] device
Deep Sleep (DS) current IDS = 22-µA maximum
Low active and standby currents
ICC = 90-mA typical
ISB2 = 20-mA typical
Wide operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V,
and 4.5 V to 5.5 V
Embedded error-correcting code (ECC) for single-bit error
correction
1.0-V data retention
Transistor-transistor logic (TTL) compatible inputs and outputs
Error indication (ERR) pin to indicate 1-bit error detection and
correction
Available in Pb-free 48-pin TSOP I, 54-pin TSOP II, and 48-ball
VFBGA packages
Functional Description
The CY7S1061G/CY7S1061GE is a high-performance CMOS
fast static RAM organized as 1,048,576 words by 16 bits. This
device features fast access times (10 ns) and a unique ultra-low
power Deep Sleep mode. With Sleep mode currents as low as
22 µA, the CY7S1061G device combines the best features of
fast and low-power SRAM in industry-standard package options.
The device also features embedded ECC[2]. ECC logic can
detect and correct single-bit error in the accessed location. The
CY7S1061GE device includes an ERR pin that signals an
error-detection and correction event during a read cycle.
To access devices with a single-chip enable input, assert the chip
enable input (CE) LOW. To access dual chip enable devices,
assert both chip enable inputs – CE1 as LOW and CE2 as HIGH.
To perform data writes, assert the Write Enable (WE) input LOW,
and provide the data and address on device data pins (I/O0
through I/O15) and address pins (A0 through A19) respectively.
The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs
control byte writes, and write data on the corresponding I/O lines
to the memory location specified. BHE controls I/O8 through
I/O15 and BLE controls I/O0 through I/O7.
To perform data reads, assert the Output Enable (OE) input and
provide the required address on the address lines. Read data is
accessible on the I/O lines (I/O0 through I/O15). You can perform
byte accesses by asserting the required byte enable signal (BHE
or BLE) to read either the upper byte or the lower byte of data
from the specified address location.
All I/Os (I/O0 through I/O15) are placed in a high-impedance state
when the device is deselected (CE HIGH for single chip enable
devices and CE1 HIGH and CE2 LOW for dual chip enable
devices), or the control signals (OE, BLE, BHE) are de-asserted.
The device is placed in a low power Deep Sleep mode when the
Deep Sleep pin (DS) is LOW. In this state, the device is disabled
for normal operation and is placed in a data retention mode. The
device can be activated by de-asserting the Deep Sleep pin (DS
HIGH).
The CY7S1061G/CY7S1061G is available in 48-pin TSOP I,
54-pin TSOP II, and 48-ball VFBGA packages.
For a complete list of related resources, click here.
Product Portfolio
Product
Range
VCC Range (V)
CY7S1061G18
CY7S1061G(E)30
CY7S1061G
Industrial
1.65 V–2.2 V
2.2 V–3.6 V
4.5–5.5 V
Speed
(ns)
15
10
10
Operating ICC
(mA)
f = fmax
Typ [3] Max
70 80
90 110
90 110
Current Consumption
Standby, ISB2 (mA) Deep-Sleep Current (µA)
Typ [3]
Max
Typ [1]
Max
20 30
8
22
Notes
1. Refer to AN89371 for details on PowerSnooze™ feature of this device.
2. This device does not support automatic write-back on error detection.
3. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V),
VCC = 3 V (for a VCC range of 2.2 V–3.6 V), and VCC = 5 V (for a VCC range of 4.5 V–5.5 V), TA = 25 °C.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-79707 Rev. *N
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 15, 2016





 CY7S1061G
Logic Block Diagram – CY7S1061G
CY7S1061G/CY7S1061GE
Logic Block Diagram – CY7S1061GE
Document Number: 001-79707 Rev. *N
Page 2 of 23





 CY7S1061G
CY7S1061G/CY7S1061GE
Contents
Pin Configurations ........................................................... 4
Maximum Ratings ............................................................. 7
Operating Range ............................................................... 7
DC Electrical Characteristics .......................................... 7
Capacitance ...................................................................... 8
Thermal Resistance .......................................................... 8
AC Test Loads and Waveforms ....................................... 8
Data Retention Characteristics ....................................... 9
Data Retention Waveform ................................................ 9
Deep-Sleep Mode Characteristics ................................. 10
AC Switching Characteristics ....................................... 11
Switching Waveforms .................................................... 12
Truth Table ...................................................................... 16
ERR Output – CY7S1061GE ........................................... 16
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 17
Package Diagrams .......................................................... 18
Acronyms ........................................................................ 21
Document Conventions ................................................. 21
Units of Measure ....................................................... 21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 23
Worldwide Sales and Design Support ....................... 23
Products .................................................................... 23
PSoC® Solutions ...................................................... 23
Cypress Developer Community ................................. 23
Technical Support ..................................................... 23
Document Number: 001-79707 Rev. *N
Page 3 of 23



Recommended third-party CY7S1061G Datasheet






@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)