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SPI nvSRAM. CY14V101Q3 Datasheet

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SPI nvSRAM. CY14V101Q3 Datasheet






CY14V101Q3 nvSRAM. Datasheet pdf. Equivalent




CY14V101Q3 nvSRAM. Datasheet pdf. Equivalent





Part

CY14V101Q3

Description

1 Mbit (128 K x 8) Serial SPI nvSRAM



Feature


CY14V101Q3 1 Mbit (128 K × 8) Serial SP I nvSRAM Features ■ 1-Mbit nonvolati le static random access memory (nvSRAM) ❐ Internally organized as 128 K × 8 ❐ STORE to QuantumTrap nonvolatile e lements initiated automatically on powe r-down (AutoStore) or by user using HSB pin (Hardware STORE) or SPI instructio n (Software STORE) ❐ RECALL to SRAM i nitiated on power-up (Power-.
Manufacture

Cypress Semiconductor

Datasheet
Download CY14V101Q3 Datasheet


Cypress Semiconductor CY14V101Q3

CY14V101Q3; Up RECALL) or by SPI instruction (Softwa re RECALL) ❐ Automatic STORE on power -down with a small capacitor ■ High r eliability ❐ Infinite read, write, an d RECALL cycles ❐ 1 million STORE cyc les to QuantumTrap ❐ Data retention: 20 years ■ High speed serial peripher al interface (SPI) ❐ 30 MHz clock rat e ❐ Supports SPI mode 0 (0,0) and mod e 3 (1,1) ■ Write protection ❐ Har.


Cypress Semiconductor CY14V101Q3

dware protection using Write Protect (WP ) pin ❐ Software protection using Wri te Disable instruction ❐ Software blo ck protection for 1/4,1/2, or entire ar ray ■ Low power consumption ❐ Core VCC = 3.0 V to 3.6 V; I/O VCCQ = .


Cypress Semiconductor CY14V101Q3

.

Part

CY14V101Q3

Description

1 Mbit (128 K x 8) Serial SPI nvSRAM



Feature


CY14V101Q3 1 Mbit (128 K × 8) Serial SP I nvSRAM Features ■ 1-Mbit nonvolati le static random access memory (nvSRAM) ❐ Internally organized as 128 K × 8 ❐ STORE to QuantumTrap nonvolatile e lements initiated automatically on powe r-down (AutoStore) or by user using HSB pin (Hardware STORE) or SPI instructio n (Software STORE) ❐ RECALL to SRAM i nitiated on power-up (Power-.
Manufacture

Cypress Semiconductor

Datasheet
Download CY14V101Q3 Datasheet




 CY14V101Q3
CY14V101Q3
1 Mbit (128 K × 8) Serial SPI nvSRAM
Features
1-Mbit nonvolatile static random access memory (nvSRAM)
Internally organized as 128 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by user using
HSB pin (Hardware STORE) or SPI instruction (Software
STORE)
RECALL to SRAM initiated on power-up
(Power-Up RECALL) or by SPI instruction
(Software RECALL)
Automatic STORE on power-down with a small capacitor
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years
High speed serial peripheral interface (SPI)
30 MHz clock rate
Supports SPI mode 0 (0,0) and mode 3 (1,1)
Write protection
Hardware protection using Write Protect (WP) pin
Software protection using Write Disable instruction
Software block protection for 1/4,1/2, or entire array
Low power consumption
Core VCC = 3.0 V to 3.6 V; I/O VCCQ = 1.65 V to 1.95 V
Average active current of 10 mA at 30 MHz operation
Industry standard configurations
Industrial temperature
16-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Functional Overview
The Cypress CY14V101Q3 combines a 1 Mbit nvSRAM with a
nonvolatile element in each memory cell with serial SPI interface.
The memory is organized as 128 K words of 8 bits each. The
embedded nonvolatile elements incorporate the QuantumTrap
technology, creating the world’s most reliable nonvolatile
memory. The SRAM provides infinite read and write cycles, while
the QuantumTrap cell provides highly reliable nonvolatile
storage of data. Data transfers from SRAM to the nonvolatile
elements (STORE operation) takes place automatically at
power-down. On power-up, data is restored to the SRAM from
the nonvolatile memory (RECALL operation). Both STORE and
RECALL operations can also be initiated by the user through SPI
instruction.
For a complete list of related documentation, click here.
Logic Block Diagram
VCC VCCQ VCAP
CS
WP
SCK
HOLD
SI
Instruction decode
Write protect
Control logic
Quantum Trap
128 K X 8
SRAM ARRAY
128 K X 8
STORE
RECALL
Instruction
register
Address
Decoder
A0-A16
D0-D7
Data I/O register
Power Control
STORE/RECALL
Control
HSB
SO
Status register
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-67191 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 13, 2014




 CY14V101Q3
CY14V101Q3
Contents
Pinouts .............................................................................. 3
Device Operation .............................................................. 4
SRAM Write ................................................................. 4
SRAM Read ................................................................ 4
STORE Operation ....................................................... 4
AutoStore Operation .................................................... 5
Software STORE Operation ........................................ 5
Hardware STORE and HSB Pin Operation ................. 5
RECALL Operation ...................................................... 5
Hardware RECALL (Power-Up) .................................. 5
Software RECALL ....................................................... 5
Disabling and Enabling AutoStore ............................... 5
Noise Considerations ....................................................... 6
Serial Peripheral Interface ............................................... 6
SPI Overview ............................................................... 6
SPI Modes ................................................................... 7
SPI Operating Features.................................................... 8
Power-Up .................................................................... 8
Power On Reset .......................................................... 8
Power-Down ................................................................ 8
Active Power and Standby Power Modes ................... 8
SPI Functional Description .............................................. 8
Status Register ................................................................. 9
Read Status Register (RDSR) Instruction ................... 9
Write Status Register (WRSR) Instruction .................. 9
Write Protection and Block Protection ......................... 10
Write Enable (WREN) Instruction .............................. 10
Write Disable (WRDI) Instruction .............................. 10
Block Protection ........................................................ 10
Write Protect (WP) Pin .............................................. 11
Memory Access .............................................................. 11
Read Sequence (READ) instruction .......................... 11
Write Sequence (WRITE) instruction ........................ 11
Software STORE (STORE) instruction ...................... 13
Software RECALL (RECALL) instruction .................. 13
AutoStore Enable (ASENB) instruction ..................... 13
AutoStore Disable (ASDISB) instruction ................... 13
HOLD Pin Operation ................................................. 14
Best Practices ................................................................. 14
Maximum Ratings ........................................................... 15
DC Electrical Characteristics ........................................ 15
Data Retention and Endurance ..................................... 16
Capacitance .................................................................... 16
Thermal Resistance ........................................................ 16
AC Test Conditions ........................................................ 16
AC Switching Characteristics ....................................... 17
AutoStore or Power-Up RECALL .................................. 18
Software Controlled STORE and RECALL Cycles ...... 19
Hardware STORE Cycle ................................................. 20
Ordering Information ...................................................... 21
Ordering Code Definition ........................................... 21
Package Diagrams .......................................................... 22
Acronyms ........................................................................ 23
Document Conventions ................................................. 23
Units of Measure ....................................................... 23
Document History Page ................................................ 24
Sales, Solutions, and Legal Information ...................... 24
Worldwide Sales and Design Support ....................... 24
Products .................................................................... 24
PSoC Solutions ......................................................... 24
Document #: 001-67191 Rev. *E
Page 2 of 24




 CY14V101Q3
CY14V101Q3
Pinouts
Figure 1. Pin Diagram – 16-pin SOIC
NC
NC
NC
NC
WP
HOLD
NC
VSS
1 16
2 15
3
CY14V101Q3
4
Top View
5 not to scale
6
14
13
12
11
7 10
89
VCC
VCCQ
VCAP
SO
SI
SCK
CS
HSB
Table 1. Pin Definitions
Pin Name
I/O Type
Description
CS
Input
Chip select. Activates the device when pulled LOW. Driving this pin high puts the device in low
power standby mode.
SCK
Input
Serial clock. Runs at speeds up to maximum of fSCK. Serial input is latched at the rising edge of
this clock. Serial output is driven at the falling edge of the clock.
SI
Input
Serial input. Pin for input of all SPI instructions and data.
SO
Output
Serial output. Pin for output of data through SPI.
WP
Input
Write protect. Implements hardware write protection in SPI.
HOLD
Input
HOLD pin. suspends serial operation.
HSB
Input/Output
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then
a weak internal pull-up resistor keeps this pin HIGH (External pull-up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
VCAP
NC
Power supply
No connect
AutoStore capacitor. Supplies power to the nvSRAM during power loss to STORE data from the
SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as No connect. It
must never be connected to VSS.
No connect: This pin is not connected to the die.
VSS
VCC
VCCQ
Power supply
Power supply
Power Supply
Ground
Power supply (3.0 V to 3.6 V)
Power supply inputs for the inputs and outputs of the device.
Document #: 001-67191 Rev. *E
Page 3 of 24






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