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I2C F-RAM. FM24CL64B Datasheet

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I2C F-RAM. FM24CL64B Datasheet






FM24CL64B F-RAM. Datasheet pdf. Equivalent




FM24CL64B F-RAM. Datasheet pdf. Equivalent





Part

FM24CL64B

Description

64-Kbit (8K x 8) Serial (I2C) F-RAM

Manufacture

Cypress Semiconductor

Datasheet
Download FM24CL64B Datasheet


Cypress Semiconductor FM24CL64B

FM24CL64B; FM24CL64B 64-Kbit (8K × 8) Serial (I2C) F-RAM 64-Kbit (8K × 8) Serial (I2C) F-RAM Features ■ 64-Kbit ferroelectri c random access memory (F-RAM) logicall y organized as 8K × 8 ❐ High-enduran ce 100 trillion (1014) read/writes ❐ 151-year data retention (See the Data R etention and Endurance table) ❐ NoDel ay™ writes ❐ Advanced high-reliabil ity ferroelectric process ■ Fast .


Cypress Semiconductor FM24CL64B

2-wire Serial interface (I2C) ❐ Up to 1-MHz frequency ❐ Direct hardware rep lacement for serial (I2C) EEPROM ❐ Su pports legacy timings for 100 kHz and 4 00 kHz ■ Low power consumption ❐ 10 0 A (typ) active current at 100 kHz ❐ 3 A (typ) standby current ■ Vo ltage operation: VDD = 2.7 V to 3.65 V ■ Industrial temperature: –40 C to +85 C ■ Packages ❐ 8-pin small outline.


Cypress Semiconductor FM24CL64B

integrated circuit (SOIC) package ❐ 8 -pin thin dual flat no leads (DFN) pack age ■ Restriction of hazardous substa nces (RoHS) compliant Functional Descr iption The FM24CL64B is a 64-Kbit nonvo latile memory emp .



Part

FM24CL64B

Description

64-Kbit (8K x 8) Serial (I2C) F-RAM

Manufacture

Cypress Semiconductor

Datasheet
Download FM24CL64B Datasheet




 FM24CL64B
FM24CL64B
64-Kbit (8K × 8) Serial (I2C) F-RAM
64-Kbit (8K × 8) Serial (I2C) F-RAM
Features
64-Kbit ferroelectric random access memory (F-RAM) logically
organized as 8K × 8
High-endurance 100 trillion (1014) read/writes
151-year data retention (See Data Retention and Endurance
on page 10)
NoDelay™ writes
Advanced high-reliability ferroelectric process
Fast 2-wire Serial interface (I2C)
Up to 1-MHz frequency
Direct hardware replacement for serial (I2C) EEPROM
Supports legacy timings for 100 kHz and 400 kHz
Low power consumption
100 A (typ) active current at 100 kHz
3 A (typ) standby current
Voltage operation: VDD = 2.7 V to 3.65 V
Industrial temperature: –40 C to +85 C
Packages
8-pin small outline integrated circuit (SOIC) package
8-pin thin dual flat no leads (DFN) package
Restriction of hazardous substances (RoHS) compliant
Functional Description
The FM24CL64B is a 64-Kbit nonvolatile memory employing an
advanced ferroelectric process. A ferroelectric random access
memory or F-RAM is nonvolatile and performs reads and writes
similar to a RAM. It provides reliable data retention for 151 years
while eliminating the complexities, overhead, and system-level
reliability problems caused by EEPROM and other nonvolatile
memories.
Unlike EEPROM, the FM24CL64B performs write operations at
bus speed. No write delays are incurred. Data is written to the
memory array immediately after each byte is successfully
transferred to the device. The next bus cycle can commence
without the need for data polling. In addition, the product offers
substantial write endurance compared with other nonvolatile
memories. Also, F-RAM exhibits much lower power during writes
than EEPROM since write operations do not require an internally
elevated power supply voltage for write circuits. The
FM24CL64B is capable of supporting 1014 read/write cycles, or
100 million times more write cycles than EEPROM.
These capabilities make the FM24CL64B ideal for nonvolatile
memory applications, requiring frequent or rapid writes.
Examples range from data logging, where the number of write
cycles may be critical, to demanding industrial controls where the
long write time of EEPROM can cause data loss. The
combination of features allows more frequent data writing with
less overhead for the system.
The FM24CL64B provides substantial benefits to users of serial
(I2C) EEPROM as a hardware drop-in replacement. The device
specifications are guaranteed over an industrial temperature
range of –40 C to +85 C.
For a complete list of related documentation, click here.
Logic Block Diagram
Counter
Address
Latch
13
SDA
SCL
WP
A2-A0
Serial to Parallel
Converter
Control Logic
8
8Kx8
F-RAM Array
8
Data Latch
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-84458 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 5, 2018





 FM24CL64B
FM24CL64B
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Functional Overview ........................................................ 4
Memory Architecture ........................................................ 4
I2C Interface ...................................................................... 4
STOP Condition (P) ..................................................... 4
START Condition (S) ................................................... 4
Data/Address Transfer ................................................ 5
Acknowledge/No-acknowledge ................................... 5
Slave Device Address ................................................. 6
Addressing Overview .................................................. 6
Data Transfer .............................................................. 6
Memory Operation ............................................................ 6
Write Operation ........................................................... 6
Read Operation ........................................................... 7
Endurance ......................................................................... 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
DC Electrical Characteristics .......................................... 9
Data Retention and Endurance ..................................... 10
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
AC Test Loads and Waveforms ..................................... 10
AC Test Conditions ........................................................ 10
AC Switching Characteristics ....................................... 11
Power Cycle Timing ....................................................... 12
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagrams .......................................................... 14
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Document Number: 001-84458 Rev. *K
Page 2 of 19





 FM24CL64B
FM24CL64B
Pinouts
Figure 1. 8-pin SOIC pinout
A0 1
8
A1 2 Top View 7
not to scale
A2 3
6
VSS 4
5
VDD
WP
SCL
SDA
Figure 2. 8-pin DFN pinout
O
A0 1
8 VDD
A1 2
A2 3
EXPOSED
PAD
7 WP
6 SCL
VSS 4
5 SDA
Top View
not to scale
Pin Definitions
Pin Name I/O Type
Description
A2–A0
SDA
SCL
Input
Device Select Address 2–0. These pins are used to select one of up to 8 devices of the same type
on the same I2C bus. To select the device, the address value on the three pins must match the
corresponding bits contained in the slave address. The address pins are pulled down internally.
Input/Output Serial Data/Address. This is a bi-directional pin for the I2C interface. It is open-drain and is intended
to be wire-AND’d with other devices on the I2C bus. The input buffer incorporates a Schmitt trigger for
noise immunity and the output driver includes slope control for falling edges. An external pull-up resistor
is required.
Input
Serial Clock. The serial clock pin for the I2C interface. Data is clocked out of the device on the falling
edge, and into the device on the rising edge. The SCL input also incorporates a Schmitt trigger input
for noise immunity.
WP
Input
Write Protect. When tied to VDD, addresses in the entire memory map will be write-protected. When
WP is connected to ground, all addresses are write enabled. This pin is pulled down internally.
VSS
VDD
EXPOSED
PAD
Power supply Ground for the device. Must be connected to the ground of the system.
Power supply Power supply input to the device.
No connect The EXPOSED PAD on the bottom of 8-pin DFN package is not connected to the die. The EXPOSED
PAD should not be soldered on the PCB.
Document Number: 001-84458 Rev. *K
Page 3 of 19



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