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Automotive F-RAM. FM25640B Datasheet

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Automotive F-RAM. FM25640B Datasheet






FM25640B F-RAM. Datasheet pdf. Equivalent




FM25640B F-RAM. Datasheet pdf. Equivalent





Part

FM25640B

Description

64-Kbit (8 K x 8) Serial (SPI) Automotive F-RAM



Feature


FM25640B 64-Kbit (8 K × 8) Serial (SPI) Automotive F-RAM 64-Kbit (8 K × 8) S erial (SPI) Automotive F-RAM Features ⠖  64-Kbit ferroelectric random access memory (F-RAM) logically organized as 8 K × 8 ❐ High-endurance 10 trillion (1013) read/writes ❐ 121-year data re tention (See the Data Retention and End urance table) ❐ NoDelay™ writes ❐ Advanced high-reliability ferroe.
Manufacture

Cypress Semiconductor

Datasheet
Download FM25640B Datasheet


Cypress Semiconductor FM25640B

FM25640B; lectric process ■ Very fast serial per ipheral interface (SPI) ❐ Up to 4 MHz frequency ❐ Direct hardware replacem ent for serial flash and EEPROM ❐ Sup ports SPI mode 0 (0, 0) and mode 3 (1, 1) ■ Sophisticated write protection s cheme ❐ Hardware protection using the Write Protect (WP) pin ❐ Software pr otection using Write Disable instructio n ❐ Software block protection fo.


Cypress Semiconductor FM25640B

r 1/4, 1/2, or entire array ■ Low powe r consumption ❐ 300 A active curre nt at 1 MHz ❐ 10 A (typ) standby c urrent at +85 C ■ Voltage operatio n: VDD = 4.5 V to 5.5 V ■ Automotive- E temperature: –40 C to +125 .


Cypress Semiconductor FM25640B

.

Part

FM25640B

Description

64-Kbit (8 K x 8) Serial (SPI) Automotive F-RAM



Feature


FM25640B 64-Kbit (8 K × 8) Serial (SPI) Automotive F-RAM 64-Kbit (8 K × 8) S erial (SPI) Automotive F-RAM Features ⠖  64-Kbit ferroelectric random access memory (F-RAM) logically organized as 8 K × 8 ❐ High-endurance 10 trillion (1013) read/writes ❐ 121-year data re tention (See the Data Retention and End urance table) ❐ NoDelay™ writes ❐ Advanced high-reliability ferroe.
Manufacture

Cypress Semiconductor

Datasheet
Download FM25640B Datasheet




 FM25640B
FM25640B
64-Kbit (8K × 8) Serial (SPI) F-RAM
64-Kbit (8K × 8) Serial (SPI) F-RAM
Features
■ 64-Kbit ferroelectric random access memory (F-RAM) logically
organized as 8K × 8
❐ High-endurance 100 trillion (1014) read/writes
❐ 151-year data retention (See Data Retention and Endurance
on page 12)
❐ NoDelay™ writes
❐ Advanced high-reliability ferroelectric process
■ Very fast serial peripheral interface (SPI)
❐ Up to 20 MHz frequency
❐ Direct hardware replacement for serial flash and EEPROM
❐ Supports SPI mode 0 (0, 0) and mode 3 (1, 1)
■ Sophisticated write protection scheme
❐ Hardware protection using the Write Protect (WP) pin
❐ Software protection using Write Disable instruction
❐ Software block protection for 1/4, 1/2, or entire array
■ Low power consumption
❐ 250 A active current at 1 MHz
❐ 4 A (typ) standby current
■ Voltage operation: VDD = 4.5 V to 5.5 V
■ Industrial temperature: –40 C to +85 C
■ 8-pin small outline integrated circuit (SOIC) package
■ Restriction of hazardous substances (RoHS) compliant
Functional Description
The FM25640B is a 64-Kbit nonvolatile memory employing an
advanced ferroelectric process. A ferroelectric random access
memory or F-RAM is nonvolatile and performs reads and writes
similar to a RAM. It provides reliable data retention for 151 years
while eliminating the complexities, overhead, and system level
reliability problems caused by serial flash, EEPROM, and other
nonvolatile memories.
Unlike serial flash and EEPROM, the FM25640B performs write
operations at bus speed. No write delays are incurred. Data is
written to the memory array immediately after each byte is
successfully transferred to the device. The next bus cycle can
commence without the need for data polling. In addition, the
product offers substantial write endurance compared with other
nonvolatile memories. The FM25640B is capable of supporting
1014 read/write cycles, or 100 million times more write cycles
than EEPROM.
These capabilities make the FM25640B ideal for nonvolatile
memory applications requiring frequent or rapid writes.
Examples range from data collection, where the number of write
cycles may be critical, to demanding industrial controls where the
long write time of serial flash or EEPROM can cause data loss.
The FM25640B provides substantial benefits to users of serial
EEPROM or flash as a hardware drop-in replacement. The
FM25640B uses the high-speed SPI bus, which enhances the
high-speed write capability of F-RAM technology. The device
specifications are guaranteed over an industrial temperature
range of –40 C to +85 C.
For a complete list of related documentation, click here.
Logic Block Diagram
WP
CS
HOLD
SCK
Instruction Decoder
Clock Generator
Control Logic
Write Protect
8Kx8
F-RAM Array
Instruction Register
Address Register
Counter
13
8
SI SO
Data I/O Register
3
Nonvolatile Status
Register
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-84468 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 6, 2018




 FM25640B
FM25640B
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Functional Overview ........................................................ 4
Memory Architecture ........................................................ 4
Serial Peripheral Interface – SPI Bus .............................. 4
SPI Overview ............................................................... 4
SPI Modes ................................................................... 5
Power Up to First Access ............................................ 6
Command Structure .................................................... 6
WREN - Set Write Enable Latch ................................. 6
WRDI - Reset Write Enable Latch ............................... 6
Status Register and Write Protection ............................. 6
RDSR - Read Status Register ..................................... 7
WRSR - Write Status Register .................................... 7
Memory Operation ............................................................ 8
Write Operation ........................................................... 8
Read Operation ........................................................... 8
HOLD Pin Operation ................................................... 9
Endurance ................................................................. 10
Maximum Ratings ........................................................... 11
Operating Range ............................................................. 11
DC Electrical Characteristics ........................................ 11
Data Retention and Endurance ..................................... 12
Capacitance .................................................................... 12
Thermal Resistance ........................................................ 12
AC Test Conditions ........................................................ 12
AC Switching Characteristics ....................................... 13
Power Cycle Timing ....................................................... 15
Ordering Information ...................................................... 16
Ordering Code Definitions ......................................... 16
Package Diagram ............................................................ 17
Acronyms ........................................................................ 18
Document Conventions ................................................. 18
Units of Measure ....................................................... 18
Document History Page ................................................. 19
Sales, Solutions, and Legal Information ...................... 21
Worldwide Sales and Design Support ....................... 21
Products .................................................................... 21
PSoC® Solutions ...................................................... 21
Cypress Developer Community ................................. 21
Technical Support ..................................................... 21
Document Number: 001-84468 Rev. *I
Page 2 of 21




 FM25640B
FM25640B
Pinout
Figure 1. 8-pin SOIC pinout
CS 1
8
SO 2 Top View 7
not to scale
WP 3
6
VSS 4
5
VDD
HOLD
SCK
SI
Pin Definitions
Pin Name
CS
SCK
SI[1]
SO[1]
WP
HOLD
VSS
VDD
I/O Type
Description
Input
Chip Select. This active LOW input activates the device. When HIGH, the device enters low-power
standby mode, ignores other inputs, and tristates the output. When LOW, the device internally
activates the SCK signal. A falling edge on CS must occur before every opcode.
Input
Serial Clock. All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge
and outputs occur on the falling edge. Because the device is synchronous, the clock frequency may
be any value between 0 and 20 MHz and may be interrupted at any time.
Input
Serial Input. All data is input to the device on this pin. The pin is sampled on the rising edge of SCK
and is ignored at other times. It should always be driven to a valid logic level to meet IDD specifications.
Output
Serial Output. This is the data output pin. It is driven during a read and remains tristated at all other
times including when HOLD is LOW. Data transitions are driven on the falling edge of the serial clock.
Input
Write Protect. This active LOW pin prevents write operation to the Status Register when WPEN is
set to ‘1’. This is critical because other write protection features are controlled through the Status
Register. A complete explanation of write protection is provided in Status Register and Write Protection
on page 7. This pin must be tied to VDD if not used. Note that the function of WP is different from the
FM25040 where it prevents all writes to the part.
Input
HOLD Pin. The HOLD pin is used when the host CPU must interrupt a memory operation for another
task. When HOLD is LOW, the current operation is suspended. The device ignores any transition on
SCK or CS. All transitions on HOLD must occur while SCK is LOW. This pin must be tied to VDD if not
used.
Power supply Ground for the device. Must be connected to the ground of the system.
Power supply Power supply inputs to the device.
Note
1. SI may be connected to SO for a single pin data interface.
Document Number: 001-84468 Rev. *I
Page 3 of 21






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