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Static RAM. CY7C1020DV33 Datasheet

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Static RAM. CY7C1020DV33 Datasheet






CY7C1020DV33 RAM. Datasheet pdf. Equivalent




CY7C1020DV33 RAM. Datasheet pdf. Equivalent





Part

CY7C1020DV33

Description

512 K (32 K x 16) Static RAM



Feature


CY7C1020DV33 512 K (32 K x 16) Static RA M A8 A9 A10 A11 A12 A13 A14 Features ■ Pin-and function-compatible with CY 7C1020CV33 ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 60 mA @ 10 ns ■ Low CMOS standby power ❐ ISB2 = 3 mA ■ 2.0 V Data retention Automatic power-down when deselected ■ CMOS for optimum speed/power ■ I ndependent control of upper and lower bi.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1020DV33 Datasheet


Cypress Semiconductor CY7C1020DV33

CY7C1020DV33; ts ■ Available in Pb-free 44-pin 400-M il wide Molded SOJ and 44-pin TSOP II p ackages Functional Description The CY7C 1020DV33 is a high-performance CMOS sta tic RAM organized as 32,768 words by 16 bits. This device has an automatic pow er-down feature that significantly redu ces power consumption when deselected. Logic Block Diagram DATA IN DRIVERS RO W DECODER SENSE AMPS.


Cypress Semiconductor CY7C1020DV33

A7 A6 A5 A4 32K x 16 A3 RAM Array A2 A1 A0 COLUMN DECODER Writing to the device is accomplished by taking c hip enable (CE) and write enable (WE) i nputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (I/O0 thro u .


Cypress Semiconductor CY7C1020DV33

.

Part

CY7C1020DV33

Description

512 K (32 K x 16) Static RAM



Feature


CY7C1020DV33 512 K (32 K x 16) Static RA M A8 A9 A10 A11 A12 A13 A14 Features ■ Pin-and function-compatible with CY 7C1020CV33 ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 60 mA @ 10 ns ■ Low CMOS standby power ❐ ISB2 = 3 mA ■ 2.0 V Data retention Automatic power-down when deselected ■ CMOS for optimum speed/power ■ I ndependent control of upper and lower bi.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1020DV33 Datasheet




 CY7C1020DV33
CY7C1020DV33
512 K (32 K x 16) Static RAM
Features
Pin-and function-compatible with CY7C1020CV33
High speed
tAA = 10 ns
Low active power
ICC = 60 mA @ 10 ns
Low CMOS standby power
ISB2 = 3 mA
2.0 V Data retention
Automatic power-down when deselected
CMOS for optimum speed/power
Independent control of upper and lower bits
Available in Pb-free 44-pin 400-Mil wide Molded SOJ and
44-pin TSOP II packages
Functional Description
The CY7C1020DV33 is a high-performance CMOS static
RAM organized as 32,768 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
Logic Block Diagram
DATA IN DRIVERS
A7
A6
A5
A4
32K x 16
A3 RAM Array
A2
A1
A0
COLUMN DECODER
Writing to the device is accomplished by taking chip enable
(CE) and write enable (WE) inputs LOW. If byte low enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A14). If byte high enable (BHE) is LOW, then data from
I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A14).
Reading from the device is accomplished by taking chip
enable (CE) and output enable (OE) LOW while forcing the
write enable (WE) HIGH. If byte low enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O0 to I/O7. If byte high enable (BHE) is LOW,
then data from memory will appear on I/O8 to I/O15. See the
truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020DV33 is available in Pb-free 44-pin 400-Mil
wide Molded SOJ and 44-pin TSOP II packages.
For a complete list of related documentation, click here.
I/O0–I/O7
I/O8–I/O15
BHE
WE
CE
OE
BLE
Pin Configuration[1]
SOJ/TSOP II
Top View
NC
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A4
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 A5
43 A6
42 A7
41 OE
40 BHE
39 BLE
38 I/O15
37 I/O14
36 I/O13
35 I/O12
34 VSS
33 VCC
32 I/O11
31 I/O10
30 I/O9
29 I/O8
28 NC
27 A8
26 A9
25 A10
24 A11
23 NC
Notes
1. NC pins are not connected on the die.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05461 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 19, 2014




 CY7C1020DV33
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
CY7C1020DV33
–10 (Industrial)
10
60
3
Unit
ns
mA
mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage temperature ................................ –65 C to +150 C
Ambient temperature with
power applied ........................................... –55 C to +125 C
Supply voltage on VCC to Relative GND[2] ...–0.5 V to +4.6 V
DC voltage applied to outputs
in High-Z State[2].................................. –0.5 V to VCC + 0.5 V
DC input voltage[2]............................... –0.5 V to VCC + 0.5 V
Current into outputs (LOW) ......................................... 20 mA
Static discharge voltage........................................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-up current ..................................................... > 200 mA
Operating Range
Range
Industrial
Ambient
Temperature
VCC
–40 °C to +85 °C 3.3 V 0.3 V
Speed
10 ns
Electrical Characteristics Over the Operating Range
Parameter
Description
VOH Output HIGH voltage
VOL Output LOW voltage
VIH Input HIGH voltage
VIL Input LOW voltage[2]
IIX Input Load current
IOZ Output leakage current
ICC VCC operating
supply current
ISB1 Automatic CE Power-down
Current—TTL Inputs
ISB2 Automatic CE Power-down
Current—CMOS Inputs
Test Conditions
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
GND < VI < VCC
GND < VI < VCC, Output Disabled
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
100 MHz
83 MHz
66 MHz
40 MHz
Max. VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fMAX
Max. VCC, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0
–10 (Industrial)
Min.
Max.
2.4
0.4
2.0
0.3
VCC + 0.3
0.8
1 +1
1 +1
60
55
45
30
10
3
Unit
V
V
V
V
A
A
mA
mA
mA
mA
mA
mA
Notes
2. VIL (min.) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns.
Document Number: 38-05461 Rev. *I
Page 2 of 13




 CY7C1020DV33
CY7C1020DV33
Capacitance[3]
Parameter
Description
CIN
COUT
Input capacitance
Output capacitance
Thermal Resistance[3]
Parameter
Description
JA Thermal resistance
(Junction to Ambient)
JC Thermal resistance
(Junction to Case)
Test Conditions
TA = 25C, f = 1 MHz, VCC = 3.3 V
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
AC Test Loads and Waveforms[4]
SOJ
59.52
36.75
Max.
8
8
TSOP II
53.91
21.24
Unit
pF
pF
Unit
C/W
C/W
OUTPUT
Z = 50
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
50
1.5 V
(a)
30 pF*
3.0 V
GND
ALL INPUT PULSES
90%
90%
10%
10%
Rise Time: 1 V/ns
(b) Fall Time: 1 V/ns
High-Z characteristics: R 317
3.3 V
OUTPUT
5 pF
R2
351
(c)
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
Document Number: 38-05461 Rev. *I
Page 3 of 13



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