CY7C1020DV33

CY7C1020DV33 512 K (32 K x 16) Static RAM A8 A9 A10 A11 A12 A13 A14 Features ■ Pin-and function-compatible with CY7C1020CV33 ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 60 mA @ 10 ns ■ Low CMOS standby power ❐ ISB2 = 3 mA ■ 2.0 V Data retention ■ Automatic power-down when deselected ■ CMOS for optimum speed/power ■ Independent control of upper and lower bits ■ Available in Pb-free 44-pin 400-Mil wide Molded SOJ and 44-pin TSOP II packages Functional Description The CY7C1020DV33 is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Logic Block Diagram DATA IN DRIVERS ROW DECODER SENSE AMPS A7 A6 A5 A4 32K x 16 A3 RAM Array A2 A1 A0 COLUMN DECODER Writing to the device is accomplished by taking chip enable (CE) and write enable (WE) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (I/O0 throu...