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Static RAM. CY7C10212CV33 Datasheet

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Static RAM. CY7C10212CV33 Datasheet






CY7C10212CV33 RAM. Datasheet pdf. Equivalent




CY7C10212CV33 RAM. Datasheet pdf. Equivalent





Part

CY7C10212CV33

Description

1-Mbit (64 K x 16) Static RAM



Feature


CY7C10212CV33 1-Mbit (64 K × 16) Static RAM 1-Mbit (64 K × 16) Static RAM Fe atures ■ Temperature ranges ❐ Autom otive-E: –40 °C to 125 °C ■ Pin a nd function compatible with CY7C10212CV 33 ■ High speed ❐ tAA = 12 ns (Auto motive-E) ■ CMOS for optimum speed an d power ■ Low active power: 325 mW (m ax) ■ Automatic power down when desel ected ■ Independent control of upper and.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C10212CV33 Datasheet


Cypress Semiconductor CY7C10212CV33

CY7C10212CV33; lower bits ■ Available in Pb-free 48- ball FBGA package Functional Descripti on The CY7C10212CV33 is a high performa nce CMOS static RAM organized as 65,536 words by 16 bits. This device has an a utomatic power down feature that signif icantly reduces power consumption when deselected. Writing to the device is ac complished by taking Chip Enable (CE) a nd Write Enable (WE).


Cypress Semiconductor CY7C10212CV33

inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 thr ough I/O7), is written into the locatio n specified on the address pins (A0 thr ough A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 th .


Cypress Semiconductor CY7C10212CV33

.

Part

CY7C10212CV33

Description

1-Mbit (64 K x 16) Static RAM



Feature


CY7C10212CV33 1-Mbit (64 K × 16) Static RAM 1-Mbit (64 K × 16) Static RAM Fe atures ■ Temperature ranges ❐ Autom otive-E: –40 °C to 125 °C ■ Pin a nd function compatible with CY7C10212CV 33 ■ High speed ❐ tAA = 12 ns (Auto motive-E) ■ CMOS for optimum speed an d power ■ Low active power: 325 mW (m ax) ■ Automatic power down when desel ected ■ Independent control of upper and.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C10212CV33 Datasheet




 CY7C10212CV33
CY7C10212CV33
1-Mbit (64 K × 16) Static RAM
1-Mbit (64 K × 16) Static RAM
Features
Temperature ranges
Automotive-E: –40 °C to 125 °C
Pin and function compatible with CY7C10212CV33
High speed
tAA = 12 ns (Automotive-E)
CMOS for optimum speed and power
Low active power: 325 mW (max)
Automatic power down when deselected
Independent control of upper and lower bits
Available in Pb-free 48-ball FBGA package
Functional Description
The CY7C10212CV33 is a high performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is
LOW, then data from I/O pins (I/O0 through I/O7), is written into
the location specified on the address pins (A0 through A15). If
Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8
through I/O15) is written into the location specified on the address
pins (A0 through A15).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. For more information, see the
Truth Table on page 9 for a complete description of Read and
Write modes.
The input and output pins (I/O0 through I/O15) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE LOW
and WE LOW).
For a complete list of related documentation, click here.
Logic Block Diagram
DATA IN DRIVERS
A7
A6
A5
A4
A3
64K x 16
RAM Array
A2
A1
A0
COLUMN DECODER
I/O0–I/O7
I/O8–I/O15
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-82303 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 18, 2014




 CY7C10212CV33
CY7C10212CV33
Contents
Selection Guide ................................................................ 3
Pin Configuration ............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Switching Characteristics ................................................ 6
Switching Waveforms ...................................................... 7
Truth Table ........................................................................ 9
Ordering Information ...................................................... 10
Ordering Code Definitions ......................................... 10
Package Diagrams .......................................................... 11
Acronyms ........................................................................ 12
Document Conventions ................................................. 12
Units of Measure ....................................................... 12
Document History Page ................................................. 13
Sales, Solutions, and Legal Information ...................... 14
Worldwide Sales and Design Support ....................... 14
Products .................................................................... 14
PSoC® Solutions ...................................................... 14
Cypress Developer Community ................................. 14
Technical Support ..................................................... 14
Document Number: 001-82303 Rev. *B
Page 2 of 14




 CY7C10212CV33
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Pin Configuration
Description
Figure 1. 48-ball FBGA pinout [1]
1 2 34 56
BLE OE A0 A1 A2 NC
I/O8 BHE A3
I/O9 I/O10 A5
A4 CE I/O0
A6 I/O2 I/O1
VSS I/O11 NC A7 I/O3 VCC
VCC I/O12 NC NC I/O4 VSS
I/O14 I/O13 A14 A15 I/O5 I/O6
I/O15 NC A12 A13 WE I/O7
NC A8 A9 A10 A11 NC
A
B
C
D
E
F
G
H
CY7C10212CV33
-12 Unit
12 ns
90 mA
10 mA
Note
1. NC pins are not connected on the die.
Document Number: 001-82303 Rev. *B
Page 3 of 14



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