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Static RAM. CY7C1061DV18 Datasheet

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Static RAM. CY7C1061DV18 Datasheet






CY7C1061DV18 RAM. Datasheet pdf. Equivalent




CY7C1061DV18 RAM. Datasheet pdf. Equivalent





Part

CY7C1061DV18

Description

16-Mbit (1M x 16) Static RAM



Feature


CY7C1061DV18 16-Mbit (1M × 16) Static R AM 16-Mbit (1 M × 16) Static RAM Feat ures ■ High Speed ❐ tAA = 15 ns ■ Low Active Power ❐ ICC = 150 mA at 6 7 MHz ■ Low complementary metal oxide semiconductor (CMOS) Standby Power ❐ ISB2 = 25 mA ■ Operating voltages of 1.7 V to 2.2 V ■ 1.5 V data retentio n ■ Automatic power-down when deselec ted ■ Transistor-transistor logic (TTL.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1061DV18 Datasheet


Cypress Semiconductor CY7C1061DV18

CY7C1061DV18; ) compatible inputs and outputs ■ Easy memory expansion with CE1 and CE2 feat ures ■ Available in Pb-free 54-pin th in small outline package (TSOP) Type II package Functional Description The CY 7C1061DV18 is a high performance CMOS S tatic RAM (SRAM) organized as 1,048,576 words by 16 bits. To write to the devi ce, enable the chip (CE1 LOW and CE2 HI GH) while forcing the .


Cypress Semiconductor CY7C1061DV18

Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/ O pins (I/O0 through I/O7), is written into the location specified on the addr ess pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I .


Cypress Semiconductor CY7C1061DV18

.

Part

CY7C1061DV18

Description

16-Mbit (1M x 16) Static RAM



Feature


CY7C1061DV18 16-Mbit (1M × 16) Static R AM 16-Mbit (1 M × 16) Static RAM Feat ures ■ High Speed ❐ tAA = 15 ns ■ Low Active Power ❐ ICC = 150 mA at 6 7 MHz ■ Low complementary metal oxide semiconductor (CMOS) Standby Power ❐ ISB2 = 25 mA ■ Operating voltages of 1.7 V to 2.2 V ■ 1.5 V data retentio n ■ Automatic power-down when deselec ted ■ Transistor-transistor logic (TTL.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1061DV18 Datasheet




 CY7C1061DV18
CY7C1061DV18
16-Mbit (1M × 16) Static RAM
16-Mbit (1 M × 16) Static RAM
Features
High Speed
tAA = 15 ns
Low Active Power
ICC = 150 mA at 67 MHz
Low complementary metal oxide semiconductor (CMOS)
Standby Power
ISB2 = 25 mA
Operating voltages of 1.7 V to 2.2 V
1.5 V data retention
Automatic power-down when deselected
Transistor-transistor logic (TTL) compatible inputs and outputs
Easy memory expansion with CE1 and CE2 features
Available in Pb-free 54-pin thin small outline package (TSOP)
Type II package
Functional Description
The CY7C1061DV18 is a high performance CMOS Static RAM
(SRAM) organized as 1,048,576 words by 16 bits.
To write to the device, enable the chip (CE1 LOW and CE2 HIGH)
while forcing the Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7),
is written into the location specified on the address pins (A0
through A19). If Byte High Enable (BHE) is LOW, then data from
I/O pins (I/O8 through I/O15) is written into the location specified
on the address pins (A0 through A19).
To read from the device, enable the chip by taking CE1 LOW and
CE2 HIGH while forcing the Output Enable (OE) LOW and the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then
data from memory appears on I/O8 to I/O15. See the Truth Table
on page 11 for a complete description of Read and Write modes.
The input/output pins (I/O0 through I/O15) are placed in a high
impedance state when the device is deselected (CE1 HIGH/CE2
LOW), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation (CE1
LOW, CE2 HIGH, and WE LOW).
The CY7C1061DV18 is available in a 54-pin TSOP II pinout.
For a complete list of related documentation, click here.
Logic Block Diagram
A0
A1
A2
AA34
A5
A6
AAA978
INPUT BUFFER
1M x 16
ARRAY
I/O0–I/O7
I/O8–I/O15
COLUMN
DECODER
BHE
WE
OE
BLE
CE2
CE1
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-08350 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 28, 2016




 CY7C1061DV18
CY7C1061DV18
Contents
Selection Guide ................................................................ 3
Pin Configurations ........................................................... 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics .......................................... 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
AC Switching Characteristics ......................................... 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC® Solutions ...................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Document Number: 001-08350 Rev. *L
Page 2 of 17




 CY7C1061DV18
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Pin Configurations
Description
Figure 1. 54-pin TSOP II pinout (Top View)
I/VOC1C2
I/O13
I/O14
VSS
I/O15
A4
A3
A2
AA01
BHE
VCCEC1
WE
CAE129
A18
A17
AA1165
I/O0
VCC
IIV//OOSS21
I/O3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 I/O11
53 VSS
52 I/O10
51 I/O9
50 VCC
49 I/O8
48 A5
47 A6
46 A7
45 A8
44 A9
43 NC
42 OE
41 VSS
40 NC
39 BLE
38 A10
37 A11
36
35
AA1132
34 A14
33 I/O7
32 VSS
31 I/O6
30 I/O5
29 VCC
28 I/O4
CY7C1061DV18
-15 Unit
15 ns
150 mA
25 mA
Document Number: 001-08350 Rev. *L
Page 3 of 17



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