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8 nvSRAM. CY14V256LA Datasheet

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8 nvSRAM. CY14V256LA Datasheet






CY14V256LA nvSRAM. Datasheet pdf. Equivalent




CY14V256LA nvSRAM. Datasheet pdf. Equivalent





Part

CY14V256LA

Description

256-Kbit (32 K x 8) nvSRAM



Feature


CY14V256LA 256-Kbit (32 K × 8) nvSRAM 256-Kbit (32 K × 8) nvSRAM Features 35 ns access time ■ Internally orga nized as 32 K × 8 ■ Hands off automa tic STORE on power down with only a sma ll capacitor ■ STORE to QuantumTrap n onvolatile elements initiated by softwa re, device pin, or AutoStore on power d own ■ RECALL to SRAM initiated by sof tware or power up ■ Infinite re.
Manufacture

Cypress Semiconductor

Datasheet
Download CY14V256LA Datasheet


Cypress Semiconductor CY14V256LA

CY14V256LA; ad, write, and recall cycles ■ 1 milli on STORE cycles to QuantumTrap ■ 20 y ear data retention ■ Core VCC = 3.0 V to 3.6 V; I/O VCCQ = 1.65 V to 1.95 V ■ Industrial temperature ■ 48-ball fine-pitch ball grid array (FBGA) packa ge ■ Pb-free and restriction of hazar dous substances (RoHS) compliance Func tional Description The Cypress CY14V256 LA is a fast static RAM, with .


Cypress Semiconductor CY14V256LA

a nonvolatile element in each memory cel l. The memory is organized as 32 K byte s of 8 bits each. The embedded nonvolat ile elements incorporate QuantumTrap te chnology, producing the world’s most reliable nonvolatile memory. The SRAM .


Cypress Semiconductor CY14V256LA

.

Part

CY14V256LA

Description

256-Kbit (32 K x 8) nvSRAM



Feature


CY14V256LA 256-Kbit (32 K × 8) nvSRAM 256-Kbit (32 K × 8) nvSRAM Features 35 ns access time ■ Internally orga nized as 32 K × 8 ■ Hands off automa tic STORE on power down with only a sma ll capacitor ■ STORE to QuantumTrap n onvolatile elements initiated by softwa re, device pin, or AutoStore on power d own ■ RECALL to SRAM initiated by sof tware or power up ■ Infinite re.
Manufacture

Cypress Semiconductor

Datasheet
Download CY14V256LA Datasheet




 CY14V256LA
CY14V256LA
256-Kbit (32 K × 8) nvSRAM
256-Kbit (32 K × 8) nvSRAM
Features
35 ns access time
Internally organized as 32 K × 8
Hands off automatic STORE on power down with only a small
capacitor
STORE to QuantumTrap nonvolatile elements initiated by
software, device pin, or AutoStore on power down
RECALL to SRAM initiated by software or power up
Infinite read, write, and recall cycles
1 million STORE cycles to QuantumTrap
20 year data retention
Core VCC = 3.0 V to 3.6 V; I/O VCCQ = 1.65 V to 1.95 V
Industrial temperature
48-ball fine-pitch ball grid array (FBGA) package
Pb-free and restriction of hazardous substances (RoHS)
compliance
Functional Description
The Cypress CY14V256LA is a fast static RAM, with a
nonvolatile element in each memory cell. The memory is
organized as 32 K bytes of 8 bits each. The embedded
nonvolatile elements incorporate QuantumTrap technology,
producing the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while independent
nonvolatile data resides in the highly reliable QuantumTrap cell.
Data transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
For a complete list of related documentation, click here.
LogLiocgBicloBclkocDkiaDgiraagmram
A5
A6
A7
A8
A9
A 11
A 12
A 13
A 14
Quantum Trap
512 X 512
STORE
STATIC RAM
ARRAY
512 X 512
RECALL
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
VCC VCCQ VCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
HSB
SOFTWARE
DETECT
-A14 A2
OE
CE
WE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-76295 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 20, 2015




 CY14V256LA
CY14V256LA
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
SRAM Read ................................................................ 4
SRAM Write................................................................. 4
AutoStore Operation.................................................... 4
Hardware STORE Operation....................................... 4
Hardware RECALL (Power-Up) .................................. 5
Software STORE......................................................... 5
Software RECALL ....................................................... 5
Preventing AutoStore .................................................. 6
Data Protection............................................................ 6
Maximum Ratings............................................................. 7
Operating Range............................................................... 7
DC Electrical Characteristics .......................................... 7
Data Retention and Endurance ....................................... 8
Capacitance ...................................................................... 8
Thermal Resistance.......................................................... 8
AC Test Loads .................................................................. 9
AC Test Conditions .......................................................... 9
AC Switching Characteristics ....................................... 10
SRAM Read Cycle .................................................... 10
SRAM Write Cycle..................................................... 10
Switching Waveforms .................................................... 11
AutoStore/Power-up RECALL ....................................... 13
Switching Waveforms .................................................... 14
Software Controlled STORE/RECALL Cycle................ 15
Switching Waveforms .................................................... 15
Hardware STORE Cycle ................................................. 16
Switching Waveforms .................................................... 16
Truth Table For SRAM Operations................................ 17
Ordering Information...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagrams.......................................................... 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support....................... 22
Products .................................................................... 22
PSoC Solutions ......................................................... 22
Document Number: 001-76295 Rev. *D
Page 2 of 22




 CY14V256LA
CY14V256LA
Pinout
Figure 1. 48-ball FBGA (6 × 10 × 1.2 mm) pinout
(× 8)
Top View
(not to scale)
12
34
56
NC OE A0 A1 A2 VCC
NC NC A3 A4 CE NC
DQ0 VCC A5
A6 NC DQ4
VSS DQ1 NC A7 DQ5 VCCQ
VCCQ DQ2 VCAP VSS DQ6 VSS
DQ3 NC A14 VSS NC DQ7
NC HSB A12 A13 WE NC
NC A8 A9 A10 A11 NC
A
B
C
D
E
F
G
H
Pin Definitions
Pin Name I/O Type
Description
A0–A14
DQ0–DQ7
WE
Input Address inputs. Used to select one of the 32,768 bytes of the nvSRAM.
Input/Output Bidirectional data I/O lines. Used as input or output lines depending on operation.
Input
Write enable input, active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
CE Input Chip enable input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE Input Output enable, active LOW. The active LOW OE input enables the data output buffers during read cycles.
I/O pins are tri-stated on deasserting OE HIGH.
VSS
VCC
VCCQ
HSB
Ground Ground for the device. Must be connected to the ground of the system.
Power supply Power supply inputs to the core of the device.
Power supply Power supply inputs for the inputs and outputs of the device.
Input/Output Hardware STORE busy (HSB). When LOW, this output indicates that a Hardware STORE is in progress.
When pulled LOW, external to the chip, it initiates a nonvolatile STORE operation. After each hardware
and software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
VCAP Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
NC No connect No connect. This pin is not connected to the die.
Document Number: 001-76295 Rev. *D
Page 3 of 22



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