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AutoStore nvSRAM. STK12C68 Datasheet

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AutoStore nvSRAM. STK12C68 Datasheet






STK12C68 nvSRAM. Datasheet pdf. Equivalent




STK12C68 nvSRAM. Datasheet pdf. Equivalent





Part

STK12C68

Description

64 Kbit (8 K x 8) AutoStore nvSRAM



Feature


Not Recommended for New Designs STK12C6 8 64 Kbit (8 K x 8) AutoStore nvSRAM F eatures ■ 25 ns, 35 ns, and 45 ns acc ess times ■ Hands off automatic STORE on power-down with external 68 µF cap acitor ■ STORE to QuantumTrap nonvola tile elements is initiated by software, hardware, or AutoStore on power-down RECALL to SRAM initiated by software or power-up ■ Unlimited re.
Manufacture

Cypress Semiconductor

Datasheet
Download STK12C68 Datasheet


Cypress Semiconductor STK12C68

STK12C68; ad, write, and recall cycles ■ 1,000,0 00 STORE cycles to QuantumTrap ■ 100 year data retention to QuantumTrap ■ Single 5 V + 10% operation ■ Commerci al and industrial temperatures ■ 28-p in (330 mil) SOIC, 28-pin (300 mil) PDI P, 28-pin (600 mil) PDIP packages ■ 2 8-pin (300 mil) CDIP and 28-pad (350 mi l) LCC packages ■ RoHS compliance Fu nctional Description The Cypress.


Cypress Semiconductor STK12C68

STK12C68 is a fast static RAM with a no nvolatile element in each memory cell. The embedded nonvolatile elements incor porate QuantumTrap technology producing the world’s most reliable nonvolatil e memory. The SRAM provides unlimited r .


Cypress Semiconductor STK12C68

.

Part

STK12C68

Description

64 Kbit (8 K x 8) AutoStore nvSRAM



Feature


Not Recommended for New Designs STK12C6 8 64 Kbit (8 K x 8) AutoStore nvSRAM F eatures ■ 25 ns, 35 ns, and 45 ns acc ess times ■ Hands off automatic STORE on power-down with external 68 µF cap acitor ■ STORE to QuantumTrap nonvola tile elements is initiated by software, hardware, or AutoStore on power-down RECALL to SRAM initiated by software or power-up ■ Unlimited re.
Manufacture

Cypress Semiconductor

Datasheet
Download STK12C68 Datasheet




 STK12C68
STK12C68
64 Kbit (8 K x 8) AutoStore nvSRAM
Features
25 ns, 35 ns, and 45 ns access times
Hands off automatic STORE on power-down with external
68 µF capacitor
STORE to QuantumTrap nonvolatile elements is initiated by
software, hardware, or AutoStore on power-down
RECALL to SRAM initiated by software or power-up
Unlimited read, write, and recall cycles
1,000,000 STORE cycles to QuantumTrap
100 year data retention to QuantumTrap
Single 5 V + 10% operation
Commercial and industrial temperatures
28-pin (330 mil) SOIC, 28-pin (300 mil) PDIP, 28-pin (600 mil)
PDIP packages
28-pin (300 mil) CDIP and 28-pad (350 mil) LCC packages
RoHS compliance
Functional Description
The Cypress STK12C68 is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control. A hardware
STORE is initiated with the HSB pin.
For a complete list of related documentation, click here.
Logic Block Diagram
A5
A6
A7
A8
A9
A 11
A 12
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
Quantum Trap
128 X 512
STORE
STATIC RAM
ARRAY
128 X 512
RECALL
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
VCC
VCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
HSB
SOFTWARE
DETECT
-A0 A12
OE
CE
WE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-51027 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 17, 2014




 STK12C68
STK12C68
Contents
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
SRAM Read ....................................................................... 4
SRAM Write ....................................................................... 4
AutoStore Operation ........................................................ 4
AutoStore Inhibit Mode .................................................... 5
Hardware STORE (HSB) Operation................................. 5
Hardware RECALL (Power-up)........................................ 5
Software STORE ............................................................... 5
Software RECALL............................................................. 6
Data Protection ................................................................. 6
Noise Considerations....................................................... 6
Hardware Protect.............................................................. 6
Low Average Active Power.............................................. 6
Preventing Store............................................................... 6
Best Practices................................................................... 7
Maximum Ratings............................................................. 8
Operating Range............................................................... 8
DC Electrical Characteristics .......................................... 8
Data Retention and Endurance ....................................... 9
Capacitance ...................................................................... 9
Thermal Resistance.......................................................... 9
AC Test Conditions .......................................................... 9
AC Switching Characteristics ....................................... 10
SRAM Read Cycle .................................................... 10
SRAM Write Cycle..................................................... 11
AutoStore or Power-up RECALL................................... 12
Software Controlled STORE/RECALL Cycle................ 13
Hardware STORE Cycle ................................................. 14
Switching Waveform ...................................................... 14
Part Numbering Nomenclature...................................... 15
Ordering Information...................................................... 15
Package Diagrams.......................................................... 16
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support....................... 22
Products .................................................................... 22
PSoC Solutions ......................................................... 22
Document Number: 001-51027 Rev. *H
Page 2 of 22




 STK12C68
Pin Configurations
Figure 1. 28-Pin SOIC/DIP and LLC
STK12C68
Pin Definitions
Pin Name Alt
I/O Type
Description
A0–A12
DQ0-DQ7
WE
Input
Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.
Input or Output Bidirectional Data I/O Lines. Used as input or output lines depending on operation.
W
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O
pins is written to the specific address location.
CE E
OE G
Input
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the I/O pins to tristate.
VSS
VCC
HSB
Ground Ground for the Device. The device is connected to ground of the system.
Power Supply Power Supply Inputs to the Device.
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
VCAP
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
Document Number: 001-51027 Rev. *H
Page 3 of 22



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