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SoftStore nvSRAM. STK11C68 Datasheet

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SoftStore nvSRAM. STK11C68 Datasheet






STK11C68 nvSRAM. Datasheet pdf. Equivalent




STK11C68 nvSRAM. Datasheet pdf. Equivalent





Part

STK11C68

Description

64-Kbit (8 K x 8) SoftStore nvSRAM



Feature


Not recommended for new designs. In prod uction to support ongoing production pr ograms only. STK11C68 64-Kbit (8 K × 8) SoftStore nvSRAM Features ■ 25 ns , 35 ns, and 45 ns access times ■ Pin compatible with industry standard SRAM s ■ Software initiated nonvolatile ST ORE ■ Unlimited Read and Write endura nce ■ Automatic RECALL to SRAM on pow er up ■ Unlimited RECALL cycl.
Manufacture

Cypress Semiconductor

Datasheet
Download STK11C68 Datasheet


Cypress Semiconductor STK11C68

STK11C68; es ■ 1,000,000 STORE cycles ■ 100 ye ar data retention ■ Single 5 V+10% op eration ■ Commercial and industrial t emperature ■ 28-pin (330 mil) SOIC pa ckage ■ 28-pin (300 mil) CDIP and 28- pad (350 mil) LCC packages ■ RoHS com pliance Functional Description The Cyp ress STK11C68 is a 64Kb fast static RAM with a nonvolatile element in each mem ory cell. The embedded nonvolati.


Cypress Semiconductor STK11C68

le elements incorporate QuantumTrap tech nology producing the world’s most rel iable nonvolatile memory. The SRAM prov ides unlimited read and write cycles, w hile independent nonvolatile data resid es in the highly reliable QuantumTrap .


Cypress Semiconductor STK11C68

.

Part

STK11C68

Description

64-Kbit (8 K x 8) SoftStore nvSRAM



Feature


Not recommended for new designs. In prod uction to support ongoing production pr ograms only. STK11C68 64-Kbit (8 K × 8) SoftStore nvSRAM Features ■ 25 ns , 35 ns, and 45 ns access times ■ Pin compatible with industry standard SRAM s ■ Software initiated nonvolatile ST ORE ■ Unlimited Read and Write endura nce ■ Automatic RECALL to SRAM on pow er up ■ Unlimited RECALL cycl.
Manufacture

Cypress Semiconductor

Datasheet
Download STK11C68 Datasheet




 STK11C68
STK11C68
64-Kbit (8 K × 8) SoftStore nvSRAM
Features
25 ns, 35 ns, and 45 ns access times
Pin compatible with industry standard SRAMs
Software initiated nonvolatile STORE
Unlimited Read and Write endurance
Automatic RECALL to SRAM on power up
Unlimited RECALL cycles
1,000,000 STORE cycles
100 year data retention
Single 5 V+10% operation
Commercial and industrial temperature
28-pin (330 mil) SOIC package
28-pin (300 mil) CDIP and 28-pad (350 mil) LCC packages
RoHS compliance
Functional Description
The Cypress STK11C68 is a 64Kb fast static RAM with a nonvol-
atile element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers under software control from SRAM to the nonvolatile
elements (the STORE operation). On power up, data is automat-
ically restored to the SRAM (the RECALL operation) from the
nonvolatile memory. RECALL operations are also available
under software control.
For a complete list of related documentation, click here.
Logic Block Diagram
A5
A6
A7
A8
A9
A 11
A 12
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
Quantum Trap
128 X 512
STORE
STATIC RAM
ARRAY
128 X 512
RECALL
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
VCC
VCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
HSB
SOFTWARE
DETECT
-A0 A12
OE
CE
WE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-50638 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 24, 2015




 STK11C68
STK11C68
Contents
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
SRAM Read ....................................................................... 4
SRAM Write ....................................................................... 4
Software STORE ............................................................... 4
Software RECALL............................................................. 4
Hardware RECALL (Power Up)........................................ 4
Hardware Protect.............................................................. 4
Noise Considerations....................................................... 4
Low Average Active Power.............................................. 4
Best Practices................................................................... 5
Maximum Ratings............................................................. 6
Operating Range............................................................... 6
DC Electrical Characteristics .......................................... 6
Data Retention and Endurance ....................................... 6
Capacitance ...................................................................... 7
Thermal Resistance.......................................................... 7
AC Test Conditions .......................................................... 7
AC Switching Characteristics ......................................... 8
SRAM Read Cycle ...................................................... 8
SRAM Write Cycle....................................................... 9
AutoStore INHIBIT or Power Up RECALL .................... 10
Software Controlled STORE/RECALL Cycle................ 11
Part Numbering Nomenclature...................................... 12
Ordering Information...................................................... 12
Package Diagrams.......................................................... 13
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support....................... 18
Products .................................................................... 18
PSoC Solutions ......................................................... 18
Document Number: 001-50638 Rev. *F
Page 2 of 18




 STK11C68
STK11C68
Pin Configurations
Figure 1. Pin Diagram – 28-Pin SOIC/DIP and 28-Pin LLC
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
(TOP)
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
NC
A8
A9
A 11
OE
A 10
CE
DQ 7
DQ 6
DQ 5
DQ4
DQ3
Pin Definitions
Pin Name
A0–A12
DQ0-DQ7
Alt
WE W
CE E
OE
VSS
VCC
G
I/O Type
Description
Input
Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.
Input or
Output
Bidirectional Data I/O Lines. Used as input or output lines depending on operation.
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the
I/O pins is written to the specific address location.
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the
chip.
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers
during read cycles. Deasserting OE HIGH causes the I/O pins to tristate.
Ground Ground for the Device. The device is connected to ground of the system.
Power Supply Power Supply Inputs to the Device.
Document Number: 001-50638 Rev. *F
Page 3 of 18



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