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AutoStore nvSRAM. STK14C88 Datasheet

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AutoStore nvSRAM. STK14C88 Datasheet






STK14C88 nvSRAM. Datasheet pdf. Equivalent




STK14C88 nvSRAM. Datasheet pdf. Equivalent





Part

STK14C88

Description

32 K x 8 AutoStore nvSRAM



Feature


STK14C88 32 K x 8 AutoStore nvSRAM Feat ures ■ 25 ns, 35 ns, and 45 ns read a ccess and R/W cycle time ■ Unlimited read/write endurance ■ Automatic nonv olatile STORE on power loss ■ Nonvola tile STORE under hardware or software c ontrol ■ Automatic RECALL to SRAM on power up ■ Unlimited RECALL cycles 1-Million STORE cycles ■ 100-year n onvolatile data retention ■ Single.
Manufacture

Cypress Semiconductor

Datasheet
Download STK14C88 Datasheet


Cypress Semiconductor STK14C88

STK14C88; 5 V + 10% power supply ■ Commercial, industrial, military temperatures ■ 3 2-Pin 300 mil SOIC (RoHS-compliant) ■ 32-Pin CDIP and LCC packages Descript ion The Cypress STK14C88 is a 256 Kb fa st static RAM with a nonvolatile Quantu m Trap storage element included with ea ch memory cell. The SRAM provides the f ast access and cycle times, ease of use , and unlimited read and.


Cypress Semiconductor STK14C88

write endurance of a normal SRAM. Data automatically transfers to the nonvolat ile storage cells when power loss is de tected (the STORE operation). On power up, data is automatically restored to t he SRAM (the RECALL operation). Both ST O .


Cypress Semiconductor STK14C88

.

Part

STK14C88

Description

32 K x 8 AutoStore nvSRAM



Feature


STK14C88 32 K x 8 AutoStore nvSRAM Feat ures ■ 25 ns, 35 ns, and 45 ns read a ccess and R/W cycle time ■ Unlimited read/write endurance ■ Automatic nonv olatile STORE on power loss ■ Nonvola tile STORE under hardware or software c ontrol ■ Automatic RECALL to SRAM on power up ■ Unlimited RECALL cycles 1-Million STORE cycles ■ 100-year n onvolatile data retention ■ Single.
Manufacture

Cypress Semiconductor

Datasheet
Download STK14C88 Datasheet




 STK14C88
STK14C88
32 K x 8 AutoStore nvSRAM
Features
25 ns, 35 ns, and 45 ns read access and R/W cycle time
Unlimited read/write endurance
Automatic nonvolatile STORE on power loss
Nonvolatile STORE under hardware or software control
Automatic RECALL to SRAM on power up
Unlimited RECALL cycles
1-Million STORE cycles
100-year nonvolatile data retention
Single 5 V + 10% power supply
Commercial, industrial, military temperatures
32-Pin 300 mil SOIC (RoHS-compliant)
32-Pin CDIP and LCC packages
Description
The Cypress STK14C88 is a 256 Kb fast static RAM with a
nonvolatile Quantum Trap storage element included with each
memory cell.
The SRAM provides the fast access and cycle times, ease of
use, and unlimited read and write endurance of a normal SRAM.
Data automatically transfers to the nonvolatile storage cells
when power loss is detected (the STORE operation). On power
up, data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
The Cypress nvSRAM is the first monolithic nonvolatile memory
to offer unlimited writes and reads. It is the highest performance,
most reliable nonvolatile memory available.
For a complete list of related documentation, click here.
Logic Block Diagram
A5
A6
A7
A8
A9
A11
A12
A13
A14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Quantum Trap
512 x 512
STATIC RAM
ARRAY
512 x 512
STORE
RECALL
VCCX VCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
HSB
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
SOFTWARE
DETECT
A0 - A13
G
E
W
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-52038 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 31, 2015




 STK14C88
STK14C88
Contents
Pin Configurations ........................................................... 3
Pin Descriptions ............................................................... 3
Absolute Maximum Ratings ............................................ 4
DC Characteristics ........................................................... 4
AC Test Conditions .......................................................... 5
Capacitance ...................................................................... 5
SRAM Read Cycles #1 and #2 ......................................... 6
SRAM Write Cycle #1 and #2 ........................................... 7
Hardware Mode Selection................................................ 8
Hardware STORE Cycle ................................................... 8
AutoStore/Power up RECALL ......................................... 9
Software STORE/RECALL Mode Selection .................. 10
Software-Controlled STORE/RECALL Cycle................ 10
nvSRAM Operation......................................................... 11
Noise Considerations..................................................... 11
SRAM Read ..................................................................... 11
SRAM Write ..................................................................... 11
Power Up RECALL ......................................................... 11
Software Nonvolatile STORE......................................... 11
Software Nonvolatile RECALL ...................................... 11
AutoStore Mode.............................................................. 11
AutoStore INHIBIT Mode................................................ 12
HSB Operation ................................................................ 12
Best Practices................................................................. 13
Preventing STORES ....................................................... 13
Hardware Protect............................................................ 13
Low Average Active Power............................................ 13
Ordering Information...................................................... 14
Commercial and Industrial Ordering Information....... 14
Military Ordering Information ..................................... 15
Package Diagrams.......................................................... 16
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................ 20
Sales, Solutions, and Legal Information ...................... 21
Worldwide Sales and Design Support....................... 21
Products .................................................................... 21
PSoC Solutions ......................................................... 21
Document Number: 001-52038 Rev. *F
Page 2 of 21




 STK14C88
Pin Configurations
Figure 1. Pin Diagram - 32-Pin 300 Mil SOIC/CDIP
VCAP
A14
A12
A7
A6
A5
A4
A3
NC
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(TOP)
32 VCC
31 HSB
30 W
29 A13
28 A8
27 A9
26 A11
25 G
24 NC
23 A10
22 E
21 DQ7
20 DQ6
19 DQ5
18 DQ4
17 DQ3
STK14C88
Figure 2. Pin Diagram - 32-Pin 450 Mil LCC
A6
A5
A4
A3
NC
A2
A1
A0
DQ0
(TOP)
A13
A8
A9
A11
G
NC
A10
E
DQ7
Pin Descriptions
Pin Name
A14-A0
DQ7-DQ0
E
W
G
VCC
HSB
VCAP
VSS
NC
I/O Description
Input
Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array.
I/O Data: Bidirectional 8-bit data bus for accessing the nvSRAM.
Input
Chip Enable: The active low E input selects the device.
Input
Write Enable: The active low W enables data on the DQ pins to be written to the address location
latched by the falling edge of E.
Input
Output Enable: The active low G input enables the data output buffers during read cycles. Deasserting
G high caused the DQ pins to tristate.
Power Supply Power: 5.0 V +10%.
I/O Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low external
to the chip, it initiates a nonvolatile STORE operation. A weak pull-up resistor keeps this pin high if not
connected (optional connection).
Power Supply AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile storage elements.
Power Supply Ground.
No Connect Unlabeled pins have no internal connections.
Document Number: 001-52038 Rev. *F
Page 3 of 21



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