LVDS Transmitter. THC63LVD823 Datasheet

THC63LVD823 Transmitter. Datasheet pdf. Equivalent


THine Electronics THC63LVD823
THC63LVD823_Rev2.0
THC63LVD823
Single(135MHz)/Dual(170MHz) Link LVDS Transmitter for SXGA/SXGA+/UXGA
General Description
The THC63LVD823 transmitter is designed to support
Single Link transmission between Host and Flat Panel
Display up to SXGA+ resolutions and Dual Link trans-
mission between Host and Flat Panel Display up to
UXGA resolutions.
The THC63LVD823 converts 48bits of CMOS/TTL
data into LVDS(Low Voltage Differential Signaling)
data stream. The transmitter can be programmed for ris-
ing edge or falling edge clocks through a dedicated pin.
In Single Link, the transmit clock frequency of
135MHz, 48bits of RGB data are transmitted at an
effective rate of 945Mbps per LVDS channel. Using a
135MHz clock, the data throughput is 472Mbytes per
second.
In Dual Link, the transmit clock frequency of 85MHz,
48bits of RGB data are transmitted at an effective rate
of 595Mbps per LVDS channel. Using a 85MHz clock,
the data throughput is 595Mbytes per second.
Features
Wide dot clock range: 25-135MHz suited for VGA,
SVGA, XGA, SXGA, SXGA+ and UXGA
PLL requires No external components
Supports Dual Link, Dual-in (TTL)/Dual-out
(LVDS) pixel up to 170MHz dot clock for UXGA
Supports Single Link, Dual-in (TTL)/Single-out
(LVDS) pixel up to 135MHz dot clock for SXGA+
Supports Single Link, Single-in (TTL)/Single-out
(LVDS) pixel up to 85MHz dot clock for XGA
Clock edge selectable
Supports Reduced swing LVDS for Low EMI
Power down mode
Low power single 3.3V CMOS design
100pin TQFP
THC63LVDM83R compatible
Block Diagram
CMOS/TTL INPUT
1st DATA
RED1
GREEN1
BLUE1
8
8
8
HSYNC
VSYNC
DE
2nd DATA
RED2
GREEN2
BLUE2
8
8
8
TRANSMITTER CLOCK IN
(25 to 85MHz)
R/F
/PDWN
8
8
8
PLL
LVDS OUTPUT
TA1 +/-
TB1 +/-
TC1 +/-
1st Link
TD1 +/-
TCLK1 +/-
(25 to 135MHz)
TA2 +/-
TB2 +/-
TC2 +/-
2nd Link
TD2 +/-
TCLK2 +/-
(25 to 85MHz)
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
1
THine Electronics, Inc.


THC63LVD823 Datasheet
Recommendation THC63LVD823 Datasheet
Part THC63LVD823
Description LVDS Transmitter
Feature THC63LVD823; THC63LVD823_Rev2.0 THC63LVD823 Single(135MHz)/Dual(170MHz) Link LVDS Transmitter for SXGA/SXGA+/UXGA.
Manufacture THine Electronics
Datasheet
Download THC63LVD823 Datasheet




THine Electronics THC63LVD823
THC63LVD823 _Rev2.0
Pin Out
B15
B16
B17
R20
R21
R22
R23
R24
R25
R26
R27
VCC
GND
G20
G21
G22
G23
G24
G25
G26
G27
B20
B21
B22
B23
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50 LVDS GND
49 TA1-
48 TA1+
47 TB1-
46 TB1+
45 LVDS VCC
44 TC1-
43 TC1+
42 TCLK1-
41 TCLK1+
40 TD1-
39 TD1+
38 LVDS GND
37 TA2-
36 TA2+
35 TB2-
34 TB2+
33 LVDS VCC
32 TC2-
31 TC2+
30 TCLK2-
29 TCLK2+
28 TD2-
27 TD2+
26 LVDS GND
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
2
THine Electronics, Inc.



THine Electronics THC63LVD823
THC63LVD823 _Rev2.0
Pin Description
Pin Name
TA1+, TA1-
TB1+, TB1-
TC1+, TC1-
TD1+, TD1-
TCLK1+, TCLK1-
TA2+, TA2-
TB2+, TB2-
TC2+, TC2-
TD2+, TD2-
TCLK2+, TCLK2-
R17 ~ R10
G17 ~ G10
B17 ~ B10
R27 ~ R20
G27 ~ G20
B27 ~ B20
DE
VSYNC
HSYNC
CLKIN
TEST1, TEST5
TEST3, TEST4
TEST2
/PDWN
6/8
OE
MODE1, MODE0
RS
Pin #
48, 49
46, 47
43, 44
39, 40
41, 42
36, 37
34, 35
31, 32
27, 28
29, 30
60, 59, 58, 57,
54, 53, 52, 51
68, 67, 66, 65,
64, 63, 62, 61
78, 77, 76, 75,
74, 73, 70, 69
86, 85, 84, 83,
82, 81, 80, 79
96, 95, 94, 93,
92, 91, 90, 89
6, 5, 2, 1, 100,
99, 98, 97
9
8
7
10
13, 22
20, 21
14
19
18
17
15, 16
12
Type
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
Description
The 1st Link. The 1st pixel output data when Dual Link.
LVDS Clock Out for 1st Link.
The 2nd Link. These pins are disabled when Single Link.
LVDS Clock Out for 2nd Link.
IN
IN The 1st Pixel Data Inputs.
IN
IN
IN The 2nd Pixel Data Inputs.
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
Data Enable Input.
Vsync Input.
Hsync Input.
Clock Input.
Test Pins.
Test Pins, must be L for normal operation.
Test Pins, must be H for normal operation.
H: Normal operation,
L: Power down (all outputs are Hi-Z)
6bit/8bit color select.
H: 6bit (TDx+/- are GND), L: 8bit.
Output enable.
H: Output enable, L: Output disable (all outputs are Hi-Z)
Pixel Data Mode.
MODE1 MODE0
LL
LH
HH
Mode
Dual Link (Dual-in/Dual-out)
Single Link (Dual-in/Single-out)
Single Link (Single-in/Single-out)
LVDS swing range select.
H: Normal range, L: Reduced range.
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
3
THine Electronics, Inc.







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