74AHC138

Preliminary 74AHC138 3-TO-8 LINE DECODER DEMULTIPLEXER Description Pin Assignments The 74AHC138 is an advanced high speed CMOS device. The device accepts a three bit binary weighted address on input pins A0, A1 and A2 and when enabled will produce one active low output with the remaining seven being high. There are two active LOW enable inputs E1 and E2, and one active HIGH enable input E3. The disabled device state results in all outputs being high. The enable state occurs with E 1 and E 2 asserted low and E3 asserted high. The multiple enable lines allow for the parallel expansion of decoders to create 4-to-16 line versions with no additional parts and 5-to-32 versions with the addition of a single inverter. Features Wide Supply Voltage Range from 2.0 V to 5.5 V Sinks or sources 8mA at Vcc = 4.5V CMOS low power consumption Schmitt Trigger Action at All Inputs Inputs accept up to 5.5 V ESD Protection Tested per JESD 22 Exceeds 200-V Machine Model (A115-A) ...