Alterable E2PROM. X28HC256 Datasheet

X28HC256 Datasheet PDF, Equivalent


Part Number

X28HC256

Description

Byte Alterable E2PROM

Manufacture

Xicor

Total Page 24 Pages
PDF Download
Download X28HC256 Datasheet


X28HC256 Datasheet
X28HC256
256K
X28HC256
5 Volt, Byte Alterable E2PROM
32K x 8 Bit
FEATURES
Access Time: 70ns
Simple Byte and Page Write
—Single 5V Supply
— No External High Voltages or VPP Control
Circuits
— Self-Timed
— No Erase Before Write
— No Complex Programming Algorithms
—No Overerase Problem
Low Power CMOS:
—Active: 60mA
—Standby: 500µA
Software Data Protection
—Protects Data Against System Level
Inadvertent Writes
High Speed Page Write Capability
Highly Reliable Direct WriteCell
—Endurance: 100,000 Write Cycles
—Data Retention: 100 Years
Early End of Write Detection
DATA Polling
—Toggle Bit Polling
PIN CONFIGURATION
DESCRIPTION
The X28HC256 is a second generation high perfor-
mance CMOS 32K x 8 E2PROM. It is fabricated with
Xicor’s proprietary, textured poly floating gate tech-
nology, providing a highly reliable 5 Volt only nonvolatile
memory.
The X28HC256 supports a 128-byte page write opera-
tion, effectively providing a 24µs/byte write cycle and
enabling the entire memory to be typically rewritten in
less than 0.8 seconds. The X28HC256 also features
DATA Polling and Toggle Bit Polling, two methods of
providing early end of write detection. The X28HC256
also supports the JEDEC standard Software Data Pro-
tection feature for protecting against inadvertent writes
during power-up and power-down.
Endurance for the X28HC256 is specified as a minimum
100,000 write cycles per byte and an inherent data
retention of 100 years.
PLASTIC DIP
CERDIP
FLAT PACK
SOIC
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 22
X28HC256
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
3859 FHD F02
LCC
PLCC
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 A9
A4 7
27 A11
A3 8
A2 9
X28HC256
26 NC
25 OE
A1 10
24 A10
A0 11
23 CE
NC 12
22 I/O7
I/O0 13
21 I/O6
14 15 16 17 18 19 20
3859 FHD F03
A2
A1
A0
I/O0
I/O1
I/O2
NC
VSS
NC
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP
X28HC256
32 A3
31 A4
30 A5
29 A6
28 A7
27 A12
26 A14
25 NC
24 VCC
23 NC
22 WE
21 A13
20 A8
19 A9
18 A11
17 OE
3859 ILL F22
©Xicor, Inc. 1991, 1995 Patents Pending
3859-2.8 8/5/97 T1/C0/D0 EW
1 Characteristics subject to change without notice

X28HC256 Datasheet
X28HC256
PIN DESCRIPTIONS
Addresses (A0–A14)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X28HC256 through
the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28HC256.
FUNCTIONAL DIAGRAM
PIN NAMES
Symbol
A0–A14
I/O0–I/O7
WE
CE
OE
VCC
VSS
NC
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
No Connect
3859 PGM T01
PIN CONFIGURATION
PGA
I/O1 I/O2 I/O3 I/O5 I/O6
12 13 15 17 18
I/O0 A0
VSS I/O4 I/O7
11 10 14 16 19
A1 A2
98
A3 A4
76
CE A10
20 21
OE A11
22 23
A5 A12 VCC A9 A8
5 2 28 24 25
A6 A7
A14 WE A13
4 3 1 27 26
X28HC256
(BOTTOM VIEW)
3859 FHD F04
A0–A14
ADDRESS
INPUTS
X BUFFERS
LATCHES AND
DECODER
Y BUFFERS
LATCHES AND
DECODER
CE
OE
WE
VCC
VSS
CONTROL
LOGIC AND
TIMING
256K-BIT
E2PROM
ARRAY
I/O BUFFERS
AND LATCHES
I/O0–I/O7
DATA INPUTS/OUTPUTS
3859 FHD F01
3859 FHD F01
2


Features Datasheet pdf X28HC256 256K X28HC256 5 Volt, Byte Alt erable E2PROM 32K x 8 Bit FEATURES Access Time: 70ns • Simple Byte and Page Write —Single 5V Supply — No External High Voltages or VPP Control C ircuits — Self-Timed — No Erase Bef ore Write — No Complex Programming Al gorithms —No Overerase Problem • Lo w Power CMOS: —Active: 60mA —Standb y: 500µA • Software Data Protection —Protects Data Against System Level I nadvertent Writes • High Speed Page W rite Capability • Highly Reliable Dir ect Write™ Cell —Endurance: 100,000 Write Cycles —Data Retention: 100 Ye ars • Early End of Write Detection DATA Polling —Toggle Bit Polling PIN CONFIGURATION DESCRIPTION The X28HC25 6 is a second generation high performan ce CMOS 32K x 8 E2PROM. It is fabricate d with Xicor’s proprietary, textured poly floating gate technology, providin g a highly reliable 5 Volt only nonvola tile memory. The X28HC256 supports a 12 8-byte page write operation, effectively providing a 24µs/byte.
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